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公开(公告)号：US12073905B2
公开(公告)日：2024-08-27
申请号：US17894528
申请日：2022-08-24
发明人： Li-Te Chang , Yu-Chung Lien , Murong Lang , Zhenming Zhou , Michael G. Miller
CPC分类号： G11C29/52 , G11C16/08 , G11C16/102 , G11C16/3404
摘要： An example method of performing memory access operations comprises: receiving a request to perform a memory access operation with respect to a set of memory cells connected to a wordline of a memory device; identifying a block family associated with the set of memory cells; determining, for each logical programming level of a plurality of logical programming levels, a corresponding default block family error avoidance (BFEA) threshold voltage offset value associated with the block family; determining a value of a data state metric associated with the set of memory cells; responsive to determining that the value of the data state metric satisfies a threshold criterion, determining, for each logical programming level of a plurality of logical programming levels, a corresponding sub-BFEA threshold voltage offset value; and performing the memory access operation by applying, for each logical programming level of the plurality of logical programming levels, a combination of the default BFEA threshold voltage value, the sub-BFEA threshold voltage value, and a corresponding base voltage level.
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公开(公告)号：US12057167B2
公开(公告)日：2024-08-06
申请号：US17897184
申请日：2022-08-28
发明人： Yu-Chung Lien , Zhenming Zhou , Murong Lang
CPC分类号： G11C16/08 , G11C16/0483 , G11C16/10
摘要： A method includes determining a boundary word line in a partial block of a flash memory device, where the partial block includes blank word lines after the boundary word line; determining a single predefined level of pure data to write in at least one of the blank word lines after the boundary word line; and writing the single predefined level of pure data to at least one of the blank word lines after the boundary word line.
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公开(公告)号：US20240233843A1
公开(公告)日：2024-07-11
申请号：US18425383
申请日：2024-01-29
发明人： Zhongguang Xu , Murong Lang , Zhenming Zhou
IPC分类号： G11C16/34
CPC分类号： G11C16/3495 , G11C16/3404
摘要： A system includes a memory device having a plurality of memory cells and a processing device operatively coupled to the memory device. The processing device is to determine to perform a rewrite on at least a portion of the plurality of memory cells. The processing device can determine that a number of rewrite operations at first subset of memory cells storing a first logic state fail to satisfy a threshold criterion. The processing device can also cause a rewrite of data stored at a second subset of memory cells storing a second logic state in response to determining the number of rewrite operations performed at the first subset of memory cells fail to satisfy the threshold criterion.
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公开(公告)号：US20240231644A1
公开(公告)日：2024-07-11
申请号：US18610770
申请日：2024-03-20
发明人： Murong Lang , Tingjun Xie , Fangfang Zhu , Zhenming Zhou , Jiangli Zhu
IPC分类号： G06F3/06
CPC分类号： G06F3/0619 , G06F3/0629 , G06F3/0679
摘要： Methods, apparatuses and systems related to managing deck-specific read levels are described. The apparatus may include a memory array having the memory cells organized into two or more decks. The apparatus can determine a delay between programming the decks. The apparatus can derive and implement the deck-specific read levels by selectively adjusting a base read level with an offset level according to the delay and/or the targeted read location.
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公开(公告)号：US12027211B2
公开(公告)日：2024-07-02
申请号：US17825439
申请日：2022-05-26
发明人： Zhongguang Xu , Tingjun Xie , Murong Lang
CPC分类号： G11C16/102 , G11C16/08 , G11C16/26 , G11C16/32 , G11C16/3404
摘要： A processing device in a memory sub-system initiates a partial block handling protocol for a closed block of a memory device. The block includes a plurality of wordlines. The processing device further sends a first programming command to the memory device to program one or more wordlines of the block with first padding data. The one or more wordlines are adjacent to a last wordline of the block programmed before the block was closed. In addition, the processing device sends a second programming command to the memory device to concurrently program a remaining set of the plurality of wordlines of the block to a threshold voltage.
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公开(公告)号：US11929127B2
公开(公告)日：2024-03-12
申请号：US17463207
申请日：2021-08-31
发明人： Zhongguang Xu , Murong Lang , Zhenming Zhou
IPC分类号： G11C16/34
CPC分类号： G11C16/3495 , G11C16/3404
摘要： A system includes a memory device having a plurality of memory cells and a processing device operatively coupled to the memory device. The processing device is to determine to perform a rewrite on at least a portion of the plurality of memory cells. The processing device can determine that a number of rewrite operations at first subset of memory cells storing a first logic state fail to satisfy a threshold criterion. The processing device can also cause a rewrite of data stored at a second subset of memory cells storing a second logic state in response to determining the number of rewrite operations performed at the first subset of memory cells fail to satisfy the threshold criterion.
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公开(公告)号：US20240071503A1
公开(公告)日：2024-02-29
申请号：US17897184
申请日：2022-08-28
发明人： Yu-Chung Lien , Zhenming Zhou , Murong Lang
CPC分类号： G11C16/08 , G11C16/0483 , G11C16/10
摘要： A method includes determining a boundary word line in a partial block of a flash memory device, where the partial block includes blank word lines after the boundary word line; determining a single predefined level of pure data to write in at least one of the blank word lines after the boundary word line; and writing the single predefined level of pure data to at least one of the blank word lines after the boundary word line.
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公开(公告)号：US20240062827A1
公开(公告)日：2024-02-22
申请号：US18234289
申请日：2023-08-15
CPC分类号： G11C16/16 , G11C16/3445 , G11C16/102 , G11C16/26
摘要： A memory device can include a memory device coupled with a processing device. The processing device causes a first erase operation to be performed at a block, where the first erase operation causes a pre-program voltage and a first erase voltage having a first magnitude to be applied to the block. The processing device causes an erase detection operation to be performed at the block. The processing device determines that the block fails to satisfy the erase detection operation responsive to causing the erase detection operation to be performed. The processing device further causes a second erase operation to be performed at the block responsive to determining that the block failed the erase detection operation, where the second erase operation causes a second erase voltage having a second magnitude to be applied to the block.
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公开(公告)号：US20240045595A1
公开(公告)日：2024-02-08
申请号：US17880213
申请日：2022-08-03
发明人： Li-Te Chang , Murong Lang , Charles See Yeung Kwong , Vamsi Pavan Rayaprolu , Seungjune Jeon , Zhenming Zhou
CPC分类号： G06F3/0616 , G06F3/0653 , G06F3/0679 , G06N20/00
摘要： A processing device in a memory sub-system determines whether a media endurance metric associated with a memory block of a memory device satisfies one or more conditions. In response to the one or more conditions being satisfied, one or more read margin levels corresponding to a page type associated with the memory device are determined. A machine learning model is applied to the one or more read margin levels to generate a margin prediction value based on the page type and a wordline group associated with the memory device. Based on the margin prediction value, the memory device is assigned to a selected bin of a set of bins. A media scan operation is executed on the memory device in accordance with a scan frequency associated with the selected bin.
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公开(公告)号：US11861178B2
公开(公告)日：2024-01-02
申请号：US17462605
申请日：2021-08-31
发明人： Zhongguang Xu , Jian Huang , Tingjun Xie , Murong Lang , Zhenming Zhou
IPC分类号： G06F3/06
CPC分类号： G06F3/0619 , G06F3/0655 , G06F3/0679
摘要： A request to perform a memory access operation on a plurality of memory cells of a memory device is receive. A request type associated with the memory access operation is determined. In response to determining that the request type associated with the request type associated with the memory access operation is a first request type, an error recovery operation associated with the first request type is performed. In response to determining that the request type associated with the memory access operation is a second request type, an error recovery operation associated with the second request type is performed.
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