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    Memory system controlling nonvolatile memory
    2.
    发明授权
    Memory system controlling nonvolatile memory 有权

    公开(公告)号：US12080352B2

    公开(公告)日：2024-09-03

    申请号：US17902279

    申请日：2022-09-02

    Applicant: Kioxia Corporation

    Inventor： Kyoka Konishi ,  Yasuyuki Ushijima ,  Hisaki Niikura ,  Eriko Akaihata

    IPC: G11C16/16 ,  G11C16/08 ,  G11C16/34 ,  G11C29/52

    CPC classification number: G11C16/16 ,  G11C16/08 ,  G11C16/3495 ,  G11C29/52

    Abstract: According to one embodiment, each time the number of program/erase cycles of a block increases by a first number of times, a controller of a memory system measures the number of error bits of data read from a plurality of memory cells connected to each of a plurality of word lines. The controller identifies a word line group including a word line corresponding to the number of error bits which is greater than a threshold. The controller selects, based on an average number of error bits of the identified word line group, a parameter set to be applied to the identified word line group from a plurality of parameter sets. The controller changes, to the selected parameter set, a parameter set defining a program operation for the identified word line group.

    SEMICONDUCTOR MEMORY DEVICE
    3.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20240290407A1

    公开(公告)日：2024-08-29

    申请号：US18363546

    申请日：2023-08-01

    Applicant: SK hynix Inc.

    Inventor： Dong Hun KWAK

    IPC: G11C16/34 ,  G11C16/04 ,  G11C16/24

    CPC classification number: G11C16/3495 ,  G11C16/0433 ,  G11C16/24

    Abstract: Provided herein may be a semiconductor memory device. The semiconductor memory device may include first holes arranged in a first direction to be spaced apart from each other by a first distance, a first drain select line coupled to first memory cell strings among first and second memory cell strings separated from each of the first holes, and a second drain select line coupled to the second memory cell strings. Identical data may be stored in the first and second memory cells coupled to a selected word line, among memory cells included in each of the first memory cell strings and memory cells included in each of the second memory cell strings.

    MANAGING TRAP-UP IN A MEMORY SYSTEM
    5.
    发明公开
    MANAGING TRAP-UP IN A MEMORY SYSTEM 审中-公开

    公开(公告)号：US20240233842A1

    公开(公告)日：2024-07-11

    申请号：US18393354

    申请日：2023-12-21

    Applicant: Micron Technology, Inc.

    Inventor： Pitamber Shukla ,  Chi Ming W. Chu ,  Avinash Rajagiri ,  Ching-Huang Lu ,  Kenneth W. Marr

    IPC: G11C16/34 ,  G11C16/08 ,  G11C16/28

    CPC classification number: G11C16/3495 ,  G11C16/08 ,  G11C16/28 ,  G11C16/3404

    Abstract: Methods, systems, and devices for managing trap-up in a memory system are described. A request to erase a block of a memory device may be received. Based on the request, a scan operation for determining whether a threshold voltage distribution for a dummy word line associated with the block satisfies one or more criteria may be performed. Based on the scan operation, whether to perform one or more program and erase cycles on the block using a first voltage level for a de-biasing operation of a program and erase (P/E) cycle may be determined. The first voltage level may be lower than a second voltage level for one or more prior de-biasing operations of one or more prior P/E cycles performed on the block. The block of memory may be managed based on whether the P/E cycling with the debiasing operation having the voltage level is performed.

    Semiconductor memory device detecting program failure, and method of operating the same
    7.
    发明授权
    Semiconductor memory device detecting program failure, and method of operating the same 有权

    公开(公告)号：US11961571B2

    公开(公告)日：2024-04-16

    申请号：US17370725

    申请日：2021-07-08

    Applicant: SK hynix Inc.

    Inventor： Jae Yeop Jung ,  Sung Hyun Hwang

    IPC: G11C16/34 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26

    CPC classification number: G11C16/3459 ,  G11C16/08 ,  G11C16/102 ,  G11C16/26 ,  G11C16/3495

    Abstract: Provided herein are a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a memory cell array, a peripheral circuit, and a control logic. The memory cell array may include a plurality of memory cells. The peripheral circuit may perform a program operation on selected memory cells coupled to a selected word line among the plurality of memory cells. The control logic may control the program operation of the peripheral circuit. The program operation may include a plurality of program loops. Each of the program loops may include a program phase and a verify phase. The verify phase may include one or more verify operations. The control logic may be further configured to count a number of the verify operations performed by the peripheral circuit in the verify phase included in one of the plurality of program loops during the program operation.

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