公开(公告)号：US20240233842A1

公开(公告)日：2024-07-11

申请号：US18393354

申请日：2023-12-21

Applicant: Micron Technology, Inc.

Inventor： Pitamber Shukla ,  Chi Ming W. Chu ,  Avinash Rajagiri ,  Ching-Huang Lu ,  Kenneth W. Marr

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/28

CPC classification number: G11C16/3495 ,  G11C16/08 ,  G11C16/28 ,  G11C16/3404

Abstract: Methods, systems, and devices for managing trap-up in a memory system are described. A request to erase a block of a memory device may be received. Based on the request, a scan operation for determining whether a threshold voltage distribution for a dummy word line associated with the block satisfies one or more criteria may be performed. Based on the scan operation, whether to perform one or more program and erase cycles on the block using a first voltage level for a de-biasing operation of a program and erase (P/E) cycle may be determined. The first voltage level may be lower than a second voltage level for one or more prior de-biasing operations of one or more prior P/E cycles performed on the block. The block of memory may be managed based on whether the P/E cycling with the debiasing operation having the voltage level is performed.