-
1.发明申请公开(公告)号：US20250069663A1
公开(公告)日：2025-02-27
申请号：US18632972
申请日：2024-04-11
Applicant: SK hynix Inc.
Inventor： Chi Wook AN
Abstract: A memory device includes: a plurality of memory cells; a peripheral circuit for performing a program operation of storing data in the plurality of memory cells; and a program operation control circuit for, in the program operation, controlling the peripheral circuit to perform a foggy program operation of increasing a threshold voltage of the plurality of memory cells to a threshold voltage corresponding to any one state among an erase state and first to sixth foggy program states, and perform a fine program operation of increasing the threshold voltage of the plurality of memory cells to any one state among the erase state and first to fifteenth fine program states.
-
公开(公告)号：US20250069660A1
公开(公告)日：2025-02-27
申请号：US18454144
申请日：2023-08-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Tal PHILOSOF , Lior KISSOS , Ariel DOUBCHAK , Amit BERMAN
Abstract: Provided are a memory system, a method of reading data and a method of finding read thresholds. The method of finding read thresholds includes: selecting a channel distribution among a plurality of channel distributions that corresponds to a read page of the memory device to be read in response to a read command; generating a Trellis diagram based on a decoding scheme and a type of the read page; determining an optimal path through the Trellis diagram using the selected channel distribution according to a dynamic programming algorithm; and finding the read thresholds from the optimal path.
-
公开(公告)号：US12230349B2
公开(公告)日：2025-02-18
申请号：US18129585
申请日：2023-03-31
Applicant: Micron Technology, Inc.
Inventor： Shashank Bangalore Lakshman , Jonathan D. Harms , Jonathan J. Strand , Sukneet Singh Basuta
Abstract: Methods, systems, and devices for imprint recovery management for memory systems are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.
-
公开(公告)号：US12230328B2
公开(公告)日：2025-02-18
申请号：US17868900
申请日：2022-07-20
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyun Seo
Abstract: A semiconductor device includes a cell area including a plurality of word lines stacked on a substrate, at least one ground select line between the plurality of word lines and substrate, and a plurality of channel structures passing through the plurality of word lines and the at least one ground select line, and a peripheral circuit area including peripheral circuits controlling the cell area. The peripheral circuits input a first ground select bias voltage to the at least one ground select line during a first program time to a program word line selected from among the plurality of word lines, and input a second ground select bias voltage having a magnitude different from the first ground select bias voltage to the at least one ground select line during a second program time, the second program voltage different from the first program voltage.
-
公开(公告)号：US12230327B2
公开(公告)日：2025-02-18
申请号：US18524458
申请日：2023-11-30
Applicant: Kioxia Corporation
Inventor： Hiroshi Maejima
Abstract: A semiconductor memory device includes a memory cell array having memory strings that include memory cells and first and second selection transistors. During a read operation, a controller applies a first voltage higher than ground to a source line, and a second voltage to a first and second selection gate lines that are connected to a selected memory string. The second voltage is also applied to the first selection gate lines connected to non-selected memory strings during a first period of the read operation. A third voltage higher than ground and lower than the second voltage is applied to the first selection gate lines connected to non-selected memory strings during a second period of the read operation subsequent to the first period.
-
Patent Agency Ranking
公开(公告)号：US20250054556A1
公开(公告)日：2025-02-13
申请号：US18231368
申请日：2023-08-08
Applicant: Western Digital Technologies, Inc.
Inventor： Jiacen Guo , Xiang Yang , Henry Chin
Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and configured to retain a threshold voltage corresponding to data states. A control means applies verification pulses of program verify voltages each associated with one of the data states to selected ones of the word lines and counts the memory cells having the threshold voltage below each of the program verify voltages targeted for each of the memory cells being programmed during each of a plurality of verify loops of a program-verify operation. The control means terminates the plurality of verify loops for the memory cells targeted for one of the data states in response to the count of the memory cells exceeding a predetermined count threshold. The predetermined count threshold is different for at least one of the data states compared to other ones of the data states.
-
公开(公告)号：US20250054549A1
公开(公告)日：2025-02-13
申请号：US18756573
申请日：2024-06-27
Applicant: Micron Technology, Inc.
Inventor： Nagendra Prasad Ganesh Rao , Paing Htet , Zhenming Zhou
Abstract: Apparatuses and methods for programming partially programmed blocks with padding are provided. One example apparatus can include a controller configured to program a first number of word lines in a block of word lines in the array of memory cells, wherein the first number of word lines is less that a total number of word lines in the block, and program a second number of word lines of the array of memory cells, wherein the second number of word lines are programmed with padding and wherein the second number of word lines are different word lines that the first number of word lines and the total number of word lines in the block includes the first and second number of word lines.
-
公开(公告)号：US20250046386A1
公开(公告)日：2025-02-06
申请号：US18362509
申请日：2023-07-31
Applicant: Western Digital Technologies, Inc.
Inventor： Jiahui Yuan , Jiacen Guo , Deepanshu Dutta
Abstract: When performing a read process, a non-volatile memory first performs a pre-read sensing of the condition of memory cells connected to neighbor word lines. While applying a first word line voltage associated with a first programmed data state to the selected word line, the memory system performs two sensing operations for the first programmed data state on selected memory cells that have neighbor memory cells on the neighbor word lines in a first condition and perform two sensing operations for the first programmed data state on selected memory cells that have neighbor memory cells on the neighbor word lines in a second condition. Based on that sensing, the data being stored in the set of selected memory cells is determined. In some embodiments, at least one of the two sensing operations for each condition includes sensing soft bit information that improves the data decoding process.
-
9.发明授权公开(公告)号：US12217802B2
公开(公告)日：2025-02-04
申请号：US17648311
申请日：2022-01-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jooyong Park , Sangwon Park , Dongjin Shin , Suchang Jeon , Seungyong Choi
Abstract: A non-volatile memory device includes a meta area having a first region storing first initial data, and second regions storing second initial data, different from each other; a user area configured to store user data; an initialization register configured to store the first initial data or update the second initial data in whole or in part; and control logic configured to perform a read operation, a program operation, or an erase operation using the initial data stored in the initialization register.
-
公开(公告)号：US20250037771A1
公开(公告)日：2025-01-30
申请号：US18918966
申请日：2024-10-17
Applicant: Kioxia Corporation
Inventor： Masanobu SHIRAKAWA , Kenta YASUFUKU , Akira YAMAGA
Abstract: A memory system includes a semiconductor memory device having memory cells arranged in rows and columns, and a controller configured to issue a write command with or without a partial page program command to the semiconductor memory device. The semiconductor memory device, in response to the write command issued without the partial page command, executes a first program operation on a page of memory cells and then a first verify operation on the memory cells of the page using a first verify voltage for all of the memory cells of the page, and in response to the write command issued with the partial page command, executes a second program operation on a subset of the memory cells of the page and then a second verify operation on the memory cells of the subset using one of several different second verify voltages corresponding to the subset.
-
-
-
-
-
-
-
-
-
Search Results
6537
records
(took 0.034 seconds)
