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公开(公告)号：US20210158875A1
公开(公告)日：2021-05-27
申请号：US17165059
申请日：2021-02-02
Applicant: SK hynix Inc.
Inventor： Un Sang LEE , Chi Wook AN
Abstract: A memory device may include: memory cells each having any one of first and second programmed states as a target programmed state; a peripheral circuit configured to perform a program operation so that each memory cell has a threshold voltage corresponding to the target programmed state; and a control circuit configured to control the peripheral circuit. The control circuit may include a program operation controller configured to control the peripheral circuit so that, during the program operation, an intermediate program operation is performed on the memory cells using an intermediate verify voltage, an additional program operation is performed on memory cells each having the second programmed state as a target programmed state if an intermediate verify operation passes, and a final program operation is performed on the memory cells such that each memory cell has a threshold voltage corresponding to the target programmed state.
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公开(公告)号：US20220189557A1
公开(公告)日：2022-06-16
申请号：US17688173
申请日：2022-03-07
Applicant: SK hynix Inc.
Inventor： Jong Woo KIM , Chi Wook AN , Un Sang LEE
Abstract: A memory device comprises a plurality of memory cells each having a threshold voltage corresponding to any one of a plurality of program states according to target data to be stored by performing a program operation, page buffers configured to store data provided from a memory controller, a data conversion controller configured to control the page buffers to convert the data into the target data including a plurality of logical page bits and a program operation controller configured to perform the program operation to store the target data in the plurality of memory cells, wherein the plurality of logical page bits include at least one logical page bit distinguishing even program states from odd program states among the plurality of program states and remaining logical page bits other than the at least one logical page bit having a same value as at least one program state among adjacent program states.
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公开(公告)号：US20210398583A1
公开(公告)日：2021-12-23
申请号：US17076504
申请日：2020-10-21
Applicant: SK hynix Inc.
Inventor： Chi Wook AN , Kyung Sub PARK , Un Sang LEE
IPC: G11C11/4072 , G11C11/408 , G11C11/4074 , G11C11/409 , G11C5/06
Abstract: The memory device includes a memory block including, a voltage generator, a pass switch group connecting or blocking the global lines and the local lines to each other or from each other in response to a block selection voltage, a decoder, and a logic circuit configured to control the decoder and the voltage generator so that the local lines are floated after initializing a channel of the strings and a voltage of the global lines is lower than a voltage of the global lines when initializing the channel of the strings, when a program operation of selected memory cells included in a selected page of the memory block is completed, the channels of the strings are initialized and the local lines are floated.
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公开(公告)号：US20210065812A1
公开(公告)日：2021-03-04
申请号：US16827109
申请日：2020-03-23
Applicant: SK hynix Inc.
Inventor： Chi Wook AN
Abstract: A memory device includes bit lines coupled to a memory block, a page buffer group selecting the bit lines in response to page buffer signals, applying a precharge voltage to selected bit lines from among the bit lines, and applying a ground voltage to unselected bit lines during a program verify operation, and a page buffer controller outputting the page buffer signals to selectively apply the precharge voltage to the bit lines according to an order of read operations on a logical page during the program verify operation.
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公开(公告)号：US20150364208A1
公开(公告)日：2015-12-17
申请号：US14572071
申请日：2014-12-16
Applicant: SK hynix Inc.
Inventor： Chi Wook AN , Min Kyu LEE
CPC classification number: G11C16/3459 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3454
Abstract: A semiconductor device includes a memory block including memory cells coupled to word lines, and an operation circuit suitable for performing a program operation and a verify operation on memory cells coupled to a selected word line, wherein, when performing the program operation, the operation circuit applies a first program allowance voltage to a bit line of a first program fail cell to keep a program fail status, and a second program allowance voltage having a voltage level different from the first program allowance voltage to a bit line of a second program fail cell to change a program pass status to a program fail status.
Abstract translation: 一种半导体器件包括：存储单元，包括耦合到字线的存储器单元;以及一个适用于对耦合到所选字线的存储器单元执行编程操作和校验操作的操作电路，其中当执行编程操作时， 将第一程序允许电压施加到第一程序故障单元的位线以保持程序失败状态，以及具有不同于第一编程允许电压的电压电平的第二程序允许电压到第二程序故障单元的位线 将程序传递状态更改为程序失败状态。
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Patent Agency Ranking
6.发明申请SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME AND METHOD OF OPERATING THE SAME 有权半导体存储器件，包括其的存储器系统及其操作方法公开(公告)号：US20140140148A1
公开(公告)日：2014-05-22
申请号：US13803493
申请日：2013-03-14
Applicant: SK HYNIX INC.
Inventor： Chi Wook AN
CPC classification number: G11C7/106 , G11C7/22 , G11C11/5642 , G11C16/0483 , G11C16/06
Abstract: A method of operating a semiconductor memory device includes performing a pre-read and a first main read to selected memory cells in response to a read request, and performing a second main read to the selected memory cells in response to a re-read request.
Abstract translation: 一种操作半导体存储器件的方法包括响应于读取请求而对所选择的存储器单元执行预读取和第一主要读取，以及响应于重新读取请求对选择的存储器单元执行第二主要读取。
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公开(公告)号：US20200160906A1
公开(公告)日：2020-05-21
申请号：US16440174
申请日：2019-06-13
Applicant: SK hynix Inc.
Inventor： Un Sang LEE , Chi Wook AN
Abstract: A storage device includes a memory device configured to perform a read operation on a selected word line among a plurality of word lines, and a memory controller configured to control the memory device to: perform the read operation, perform a read retry operation on the selected word line, changing a read voltage level, when the read operation fails, and perform an additional read retry operation on the selected word line, changing the read voltage level and an application time of voltages related to the read operation, depending on whether the selected word line is a set word line, when the read retry operation fails.
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公开(公告)号：US20190221270A1
公开(公告)日：2019-07-18
申请号：US16117388
申请日：2018-08-30
Applicant: SK hynix Inc.
Inventor： Chi Wook AN
CPC classification number: G11C16/26 , G11C16/0483 , G11C16/34 , G11C16/3418 , G11C16/3495 , H01L27/11582
Abstract: There are provided a memory system and an operating method thereof. A memory system includes: a memory device including a plurality of memory blocks, the memory device configured to perform a read operation on a selected memory block among the plurality of memory blocks; and a memory controller for controlling the memory device to perform the read operation, wherein an initial turn-on period of the read operation is controlled based on information on an erase number of source line sharing blocks of the selected memory block.
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公开(公告)号：US20190214093A1
公开(公告)日：2019-07-11
申请号：US16117335
申请日：2018-08-30
Applicant: SK hynix Inc.
Inventor： Chi Wook AN
CPC classification number: G11C16/26 , G06F3/0604 , G06F3/0659 , G06F3/0679 , G11C11/5671 , G11C16/0466 , G11C16/32
Abstract: There are provided a memory system and an operating method thereof. A memory system includes: a memory device including a plurality of memory blocks configured with a plurality of pages, the memory device performing a read operation in units of pages; and a memory controller configured to control the memory device to perform the read operation, wherein the memory device is controlled such that a first initial turn-on time of a turn-on voltage for a first selected page among the plurality of pages and a second turn-on time of the turn-on voltage for subsequently selected pages are different from each other.
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10.发明申请公开(公告)号：US20250069663A1
公开(公告)日：2025-02-27
申请号：US18632972
申请日：2024-04-11
Applicant: SK hynix Inc.
Inventor： Chi Wook AN
Abstract: A memory device includes: a plurality of memory cells; a peripheral circuit for performing a program operation of storing data in the plurality of memory cells; and a program operation control circuit for, in the program operation, controlling the peripheral circuit to perform a foggy program operation of increasing a threshold voltage of the plurality of memory cells to a threshold voltage corresponding to any one state among an erase state and first to sixth foggy program states, and perform a fine program operation of increasing the threshold voltage of the plurality of memory cells to any one state among the erase state and first to fifteenth fine program states.
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