公开(公告)号：US12020753B2

公开(公告)日：2024-06-25

申请号：US18359764

申请日：2023-07-26

Applicant: Kioxia Corporation

Inventor： Naoya Tokiwa

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/26 ,  G11C16/34 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10

CPC classification number: G11C16/16 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3445 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10

Abstract: A semiconductor memory device includes a memory block, a plurality of bit lines, a plurality of select gate lines, a plurality of word lines, and a controller. The memory block includes a plurality of memory strings, each memory string including a selection transistor and a plurality of memory cells. The plurality of bit lines are arranged in the first direction and connected to the respective memory strings. The plurality of select gate lines are arranged in the second direction and connected to gates of the respective selection transistors of the memory strings. The plurality of word lines are arranged in the third direction and connected to gates of the respective memory cells of the memory strings. The controller is configured to perform an erase operation in a unit of the memory block, and perform a sequence of erase verify operations.

公开(公告)号：US20240161837A1

公开(公告)日：2024-05-16

申请号：US18420073

申请日：2024-01-23

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Eli Harari

IPC: G11C16/34 ,  G06F17/16 ,  G06N3/063 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  H01L21/28 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/786 ,  H01L29/792 ,  H01L29/92 ,  H10B43/27

CPC classification number: G11C16/3431 ,  G06F17/16 ,  G06N3/063 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0416 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/0491 ,  G11C16/10 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/40117 ,  H01L29/66833 ,  H01L29/78633 ,  H01L29/7926 ,  H01L29/92 ,  H10B43/27 ,  H10B43/10

Abstract: A 3-dimensional array of NOR memory strings being organized by planes of NOR memory strings, in which (i) the storage transistors in the NOR memory strings situated in a first group of planes are configured to be programmed, erased, program-inhibited or read in parallel, and (ii) the storage transistors in NOR memory strings situated within a second group of planes are configured for storing resource management data relating to data stored in the storage transistors of the NOR memory strings situated within the first group of planes, wherein the storage transistors in NOR memory strings in the second group of planes are configured into sets.

公开(公告)号：US11972340B2

公开(公告)日：2024-04-30

申请号：US17009066

申请日：2020-09-01

Applicant: Kwangwoon University Industry-Academic Collaboration Foundation

Inventor： In Young Chung

IPC: G11C16/16 ,  G06N3/04 ,  G06N3/063 ,  G11C16/04 ,  H10B43/27

CPC classification number: G06N3/04 ,  G06N3/063 ,  G11C16/0466 ,  H10B43/27

Abstract: Disclosed are a weight memory device capable of supporting artificial neural network operation and a weight memory system using the same. A weight memory device according to an embodiment of the present invention includes: an input terminal; a common output terminal; and charge storage disposed between the input terminal and the common output terminal, and configured to store charge. In this case, the capacitance between the input terminal and the common output terminal is determined based on the amount of charge stored in the charge storage, and is quantified based on given data to be stored in the weight memory device.

公开(公告)号：US20240136445A1

公开(公告)日：2024-04-25

申请号：US18364240

申请日：2023-08-01

Applicant: SK hynix Inc. ,  Korea Advanced Institute of Science and Technology

Inventor： Yang Kyu CHOI ,  Ji Man YU ,  Seong-Yeon KIM

IPC: H01L29/792 ,  G11C16/04 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/792 ,  G11C16/0466 ,  H01L29/40117 ,  H01L29/42348 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833

Abstract: A synapse device, a manufacturing method thereof, and a neuromorphic device including the synapse device are disclosed. The synapse device may include a channel member, a tunnel insulating layer disposed on the channel member, a charge trap layer disposed on the tunnel insulating layer, a blocking insulating layer disposed on the charge trap layer, a gate electrode disposed on the blocking insulating layer, a first terminal and a second terminal respectively connected to first and second regions of the channel member, and first and second conductors respectively bonded to the first and second terminals The charge trap layer may have a multilayer structure including a first trap layer disposed adjacent to the channel member and a second trap layer disposed adjacent to the gate electrode. The first trap layer may have a trap of a shallower level than that of the second trap layer.

公开(公告)号：US11935603B2

公开(公告)日：2024-03-19

申请号：US17572881

申请日：2022-01-11

Applicant: Infineon Technologies LLC

Inventor： Amichai Givant ,  Idan Koren ,  Shivananda Shetty ,  Pawan Singh ,  Yoram Betser ,  Kobi Danon ,  Amir Rochman

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/14 ,  G11C16/26

CPC classification number: G11C16/344 ,  G11C16/0425 ,  G11C16/0466 ,  G11C16/08 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3459

Abstract: A non-volatile memory has an array of non-volatile memory cells, first reference word lines and second reference word lines, and sense amplifiers. The sense amplifiers read system data, that has been written to supplemental non-volatile memory cells of the first reference word lines, using comparison of the supplemental non-volatile memory cells of the first reference word lines to supplemental non-volatile memory cells of the second reference word lines. Status of erasure of the non-volatile memory cells of the array is determined based on reading the system data.

公开(公告)号：US11903203B2

公开(公告)日：2024-02-13

申请号：US17461518

申请日：2021-08-30

Applicant: MACRONIX International Co., Ltd.

Inventor： Min-Feng Hung ,  Li-Yen Liang ,  Chia-Tze Huang

IPC: H01L27/11582 ,  H10B43/27 ,  H10B43/10 ,  G11C16/04

CPC classification number: H10B43/27 ,  H10B43/10 ,  G11C16/0466

Abstract: A 3D AND flash memory device includes a gate stack structure, a channel pillar, a first and a second conductive pillars, a charge storage structure, and a protective cap. The gate stack structure is disposed on a dielectric substrate and includes gate layers and insulating layers alternately stacked with each other. The channel pillar penetrates through the gate stack structure. The first and the second conductive pillars are disposed in the channel pillar and penetrate through the gate stack structure, and the first and the second conductive pillars are separated from each other and each connected to the channel pillar. The charge storage structure is disposed between the gate layers and a sidewall of the channel pillar. The protective cap covers at least a top surface of the channel pillar and isolates the first conductive pillar and the second conductive pillar from a top gate layer of the gate layers.

公开(公告)号：US11862245B2

公开(公告)日：2024-01-02

申请号：US17960441

申请日：2022-10-05

Applicant: Zeno Semiconductor, Inc.

Inventor： Yuniarto Widjaja

IPC: G11C11/34 ,  G11C14/00 ,  H01L21/28 ,  G11C11/404 ,  G11C16/04 ,  H01L27/105 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H10B12/00 ,  H10B41/30 ,  H10B41/40 ,  H10B41/42 ,  H10B43/30 ,  H10B43/40 ,  G11C16/22 ,  H01L29/06 ,  H01L21/84 ,  H01L27/12

CPC classification number: G11C14/0018 ,  G11C11/404 ,  G11C16/0408 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/225 ,  H01L27/105 ,  H01L29/0649 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/7841 ,  H01L29/7885 ,  H01L29/7887 ,  H01L29/792 ,  H01L29/7923 ,  H10B12/00 ,  H10B12/20 ,  H10B12/50 ,  H10B41/30 ,  H10B41/40 ,  H10B41/42 ,  H10B43/30 ,  H10B43/40 ,  G11C2211/4016 ,  H01L21/84 ,  H01L27/1203 ,  H10B12/056 ,  H10B12/36

Abstract: Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.

公开(公告)号：US20230290418A9

公开(公告)日：2023-09-14

申请号：US17934965

申请日：2022-09-23

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Eli Harari

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/04 ,  H01L29/10 ,  H01L29/08 ,  H01L29/786 ,  H01L29/92 ,  H01L27/11582 ,  G11C16/10 ,  H01L21/28 ,  H01L29/66 ,  H01L29/792 ,  G06F17/16 ,  G06N3/063

CPC classification number: G11C16/3431 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  H01L29/1037 ,  H01L29/0847 ,  H01L29/78633 ,  H01L29/92 ,  H01L27/11582 ,  G11C16/10 ,  H01L29/40117 ,  G11C16/0416 ,  G11C16/0491 ,  H01L29/66833 ,  H01L29/7926 ,  G11C16/0466 ,  G06F17/16 ,  G06N3/063 ,  H01L27/11565

Abstract: A 3-dimensional array of NOR memory strings being organized by planes of NOR memory strings, in which (i) the storage transistors in the NOR memory strings situated in a first group of planes are configured to be programmed, erased, program-inhibited or read in parallel, and (ii) the storage transistors in NOR memory strings situated within a second group of planes are configured for storing resource management data relating to data stored in the storage transistors of the NOR memory strings situated within the first group of planes, wherein the storage transistors in NOR memory strings in the second group of planes are configured into sets.

公开(公告)号：US20230270025A1

公开(公告)日：2023-08-24

申请号：US17676708

申请日：2022-02-21

Applicant: Micron Technology, Inc.

Inventor： Dale W. Collins ,  Paolo Fantini ,  Lorenzo Fratin ,  Enrico Varesi

IPC: G11C16/10 ,  G11C16/04 ,  C01B19/04 ,  C01B17/02

CPC classification number: G11C16/102 ,  G11C16/045 ,  C01B19/04 ,  C01B17/0243 ,  G11C16/0466 ,  G11C2216/02

Abstract: Methods, systems, and devices for chalcogenide memory device compositions are described. A memory cell may use a chalcogenide material having a composition as described herein as a storage materials, a selector materials, or as a self-selecting storage material. A chalcogenide material as described herein may include a sulfurous component, which may be completely sulfur (S) or may be a combination of sulfur and one or more other elements, such as selenium (Se). In addition to the sulfurous component, the chalcogenide material may further include one or more other elements, such as germanium (Ge), at least one Group-III element, or arsenic (As).

公开(公告)号：US20230197808A1

公开(公告)日：2023-06-22

申请号：US18079081

申请日：2022-12-12

Applicant: eMemory Technology Inc.

Inventor： Chia-Jung HSU ,  Wein-Town SUN

IPC: H01L29/423 ,  H10B43/30 ,  H01L29/792 ,  H01L29/78 ,  H10B43/10 ,  G11C16/04 ,  G11C16/14 ,  G11C16/26

CPC classification number: H01L29/4234 ,  H01L27/11568 ,  H01L29/792 ,  H01L29/7833 ,  H01L27/11565 ,  G11C16/0466 ,  G11C16/14 ,  G11C16/26 ,  H01L29/66833

Abstract: A memory cell of a charge-trapping non-volatile memory includes a semiconductor substrate, a well region, a first doped region, a second doped region, a gate structure, a protecting layer, a charge trapping layer, a dielectric layer, a first conducting line and a second conducting line. The first doped region and the second doped region are formed under a surface of the well region. The gate structure is formed over the surface of the well region. The protecting layer formed on the surface of the well region. The charge trapping layer covers the surface of the well region, the gate structure and the protecting layer. The dielectric layer covers the charge trapping layer. The first conducting line is connected with the first doped region. The second conducting line is connected with the second doped region.