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公开(公告)号：US20250062765A1
公开(公告)日：2025-02-20
申请号：US18757441
申请日：2024-06-27
Applicant: eMemory Technology Inc.
Inventor： Dung Le Tan Hoang
IPC: H03K19/0185 , H03K3/356 , H03K19/00
Abstract: A level shifter which includes an inverter, first/second/third/fourth N-type transistors, first/second P-type transistors and a buffer is provided. The inverter inverts an input voltage to generate an inverted input voltage based on a first reference voltage. The first N-type transistor has a gate receiving the input voltage. The second N-type transistor has a gate receiving the inverted input voltage. The third N-type transistor has a source coupled to a drain of the first N-type transistor. The fourth N-type transistor has a source coupled to a drain of the second N-type transistor. Gates of the first/second P-type transistors are coupled to the drains of the second/first N-type transistors, respectively, and sources of the first/second P-type transistors receive a second reference voltage. The level shifter generates an output voltage according to a shifted voltage on the drain terminal of the third N-type transistor or the drain terminal of the fourth N-type transistor.
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公开(公告)号：US20250024668A1
公开(公告)日：2025-01-16
申请号：US18670762
申请日：2024-05-22
Applicant: eMemory Technology Inc.
Inventor： Yi-Hung LI , Chun-Hung LIN
IPC: H10B20/25 , H01L29/417 , H01L29/78
Abstract: An antifuse-type memory includes a first memory cell. The first memory cell includes a first select transistor, a first following transistor and a first antifuse transistor. A first drain/source terminal of the first select transistor is connected with a first bit line. A gate terminal of the first select transistor is connected with a first word line. A first drain/source terminal of the first following transistor is connected with a second drain/source terminal of the first select transistor. A gate terminal of the first following transistor is connected with a first following control line. The first antifuse transistor includes a first fin, a first gate structure, a first drain/source contact layer and a second drain/source contact layer. The first gate structure includes a first gate dielectric layer and a first gate layer. The first gate layer is connected with a first antifuse control line.
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公开(公告)号：US20250023567A1
公开(公告)日：2025-01-16
申请号：US18660251
申请日：2024-05-10
Applicant: eMemory Technology Inc.
Inventor： Wei-Chiang ONG , Cheng-Yu CHUNG
IPC: H03K19/0185 , H03K3/012 , H03K3/356
Abstract: A level shifting circuit includes a first-type level shifter, a second-type level shifter and a controller. The controller is connected to the output terminal of the first-type level shifter and the output terminal of the second-type level shifter. The level shifting circuit can be operated in different modes. In a standby mode, the logic level state of an output signal from the level shifting circuit is determined according to the logic level state of a shifted signal from the first-type level shifter. In a non-standby mode, the logic level state of the output signal from the level shifting circuit is determined according to the logic level state of a shifted signal from the second-type level shifter.
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公开(公告)号：US20240420745A1
公开(公告)日：2024-12-19
申请号：US18629972
申请日：2024-04-09
Applicant: eMemory Technology Inc.
Inventor： Wei-Ming KU
Abstract: A sense amplifier for a non-volatile memory is provided. A first memory cell of the non-volatile memory is coupled to a data line. The sense amplifier includes a first switching device, a first voltage boosting circuit and a comparator. A first terminal of the first switching device is connected with the data line. A second terminal of the first switching device is connected with a ground terminal. A control terminal of the first switching device receives a reset signal. An input terminal of the first voltage boosting circuit is connected with the data line. An output terminal of the first voltage boosting circuit is connected with a sensing node. A first input terminal of the comparator receives a comparison voltage. A second input terminal of the comparator is connected with the sensing node. An output terminal of the comparator generates an output data.
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公开(公告)号：US20240395342A1
公开(公告)日：2024-11-28
申请号：US18417389
申请日：2024-01-19
Applicant: eMemory Technology Inc.
Inventor： Chia-Jung HSU , Yun-Jen Ting , Cheng-Heng Chung , Chun-Hsiao Li , Tsung-Mu Lai
Abstract: A non-volatile memory cell includes a select transistor and a memory transistor. The first drain/source terminal of the select transistor is connected with a first control terminal. The second drain/source terminal of the select transistor is connected with the first drain/source terminal of the memory transistor. The gate terminal of the select transistor is connected with a select gate terminal. The second drain/source terminal of the memory transistor is connected with a second control terminal. The gate terminal of the memory transistor is connected with a memory gate terminal. During a program action, the select transistor is turned on, and a tapered channel is formed in the memory transistor. The tapered channel is pinched off near the first drain/source terminal of the memory transistor, and plural hot carriers near a pinch off point are injected into the charge storage layer.
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Patent Agency Ranking
公开(公告)号：US20240161844A1
公开(公告)日：2024-05-16
申请号：US18370412
申请日：2023-09-20
Applicant: eMemory Technology Inc.
Inventor： Chia-Fu CHANG , Jen-Yu PENG , Ming-Hsuan TAN
Abstract: An antifuse-type non-volatile memory and a control method for the antifuse-type non-volatile memory are provided. During a program action of a program cycle, a timing controller generates a timing control signal. According to the timing control signal, a word line driver is controlled to provide an on voltage and an off voltage to an activated word line. In a total time period of plural on periods, the program current is sufficient to rupture a gate oxide layer of an antifuse transistor in the selected memory cell, and a heating process is completed. Consequently, the gate oxide layer of the antifuse transistor is in a solid rupture state. Consequently, the program action can be successfully performed on the selected memory cell.
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公开(公告)号：US20240161843A1
公开(公告)日：2024-05-16
申请号：US18370404
申请日：2023-09-20
Applicant: eMemory Technology Inc.
Inventor： Chia-Fu Chang , Chun-Hung Lin , Jen-Yu Peng , You-Ruei Chuang
Abstract: An anti-fuse memory device includes an anti-fuse module, a reference current circuit and a controller. A write enable signal enables a write controller and a write buffer of the anti-fuse module to program a selected anti-fuse memory cell in an anti-fuse array of the anti-fuse module, and a timing controller of the anti-fuse module stops a program operation of the anti-fuse array after a sense amplifier of the anti-fuse module changes a state of a readout data signal for a predetermined time duration.
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公开(公告)号：US20240161811A1
公开(公告)日：2024-05-16
申请号：US18387476
申请日：2023-11-07
Applicant: eMemory Technology Inc.
Inventor： Hsin-Chan PENG
IPC: G11C11/4091 , G11C11/4093 , G11C11/4096
CPC classification number: G11C11/4091 , G11C11/4093 , G11C11/4096
Abstract: A latch type sense amplifier includes three transistors, a latching device and two capacitors. The two drain/source terminals of the first transistor are connected with a first node and a second node. The gate terminal of the first transistor receives a reference voltage. The two drain/source terminals of the second transistor are connected with the first node and a third node. The gate terminal of the second transistor is connected with a data line. The two drain/source terminals of the third transistor are connected with a first supply voltage and the first node. The gate terminal of the third transistor receives an enable signal. The latching device is connected with the second node and the third node. The first capacitor is connected between gate terminals of the third transistor and the first transistor. The second capacitor is connected between gate terminals of the third transistor and the second transistor.
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公开(公告)号：US20240160238A1
公开(公告)日：2024-05-16
申请号：US18361900
申请日：2023-07-30
Applicant: eMemory Technology Inc.
Inventor： Che-Wei CHANG
CPC classification number: G05F1/575 , H02M3/1584 , H02M1/14
Abstract: A regulator includes a pre-regulator circuit, a pump circuit, an output stage circuit, and a tracking circuit. The pre-regulator circuit is configured to generate a pre-regulated voltage according to a power voltage. The pump circuit is configured to generate a pumped voltage according to the pre-regulated voltage and a tracking voltage. The output stage circuit is configured to generate an output voltage according to the pumped voltage and the power voltage. The tracking circuit is configured to track the output stage circuit to generate the tracking voltage and transmit the tracking voltage to the pump circuit.
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公开(公告)号：US20240095411A1
公开(公告)日：2024-03-21
申请号：US18243683
申请日：2023-09-08
Applicant: eMemory Technology Inc.
Inventor： Dung Le Tan Hoang
CPC classification number: G06F21/755 , G06F21/554 , H03K19/20 , G06F2221/034
Abstract: A fault-injection protection circuit includes a circuit under protection and a detection circuit. The detection circuit includes a detection cell having unequal pull-up capability and pull-down capability, and is arranged at a distance less than a laser spot diameter from the circuit under protection. The detection circuit is used to generate an alarm signal upon detecting a laser fault injection.
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