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公开(公告)号：US20210074855A1
公开(公告)日：2021-03-11
申请号：US17013869
申请日：2020-09-08
Applicant: eMemory Technology Inc.
Inventor： Chih-Hsin Chen , Shih-Chen Wang , Tsung-Mu Lai , Wen-Hao Ching , Chun-Yuan Lo , Wei-Chen Chang
Abstract: A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure.
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公开(公告)号：US20190164981A1
公开(公告)日：2019-05-30
申请号：US16001933
申请日：2018-06-06
Applicant: eMemory Technology Inc.
Inventor： Chih-Hsin Chen , Tsung-Mu Lai , Shih-Chen Wang
IPC: H01L27/11524 , H01L29/423 , H01L29/49 , H01L29/06 , G11C11/56 , G11C16/04
Abstract: A multi-cell per bit nonvolatile memory (NVM) unit includes a select transistor disposed on a first oxide define (OD) region, a word line transistor disposed on the first OD region, and serially connected floating gate transistors disposed between the select transistor and the word line transistor. A first floating gate extension continuously extends toward a second OD region and adjacent to an erase gate region. A second floating gate extension continuously extends toward a third OD region and is capacitively coupled to a control gate region. A channel length of each of the floating gate transistors is shorter than that of the select transistor or the word line transistor.
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公开(公告)号：US20180190357A1
公开(公告)日：2018-07-05
申请号：US15905802
申请日：2018-02-26
Applicant: eMemory Technology Inc.
Inventor： Tsung-Mu Lai , Wen-Hao Ching , Chen-Hao Po
IPC: G11C16/12 , G11C16/08 , H01L27/11521 , G11C16/24 , G11C16/14
CPC classification number: G11C16/30 , G11C7/065 , G11C7/10 , G11C7/12 , G11C7/22 , G11C8/10 , G11C16/0408 , G11C16/0433 , G11C16/0458 , G11C16/08 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/16 , G11C16/24 , G11C16/26 , H01L23/528 , H01L27/0207 , H01L27/11517 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11558 , H01L27/1203 , H01L29/0649 , H01L29/0847 , H01L29/1095 , H01L29/42328
Abstract: A memory array includes a plurality of memory pages, each memory page includes a plurality of memory cells, and each memory cell includes a floating gate module, a control element, and an erase element. The floating gate module is disposed in a first well, the erase element is disposed in a second well, and the control element is disposed in a third well. The first well, the second well and the third well are disposed in a deep doped region, and memory cells of the plurality of memory pages are all disposed in the deep doped region. Therefore, the spacing rule between deep doped regions is no longer be used to limit the circuit area of the memory array and the circuit area of the memory array can be reduced.
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公开(公告)号：US09041089B2
公开(公告)日：2015-05-26
申请号：US14141428
申请日：2013-12-27
Applicant: eMemory Technology Inc.
Inventor： Chih-Hsin Chen , Wei-Ren Chen , Tsung-Mu Lai
IPC: H01L29/788 , H01L27/115
CPC classification number: H01L27/11524 , G11C16/0425 , H01L27/11519 , H01L27/1156
Abstract: A nonvolatile memory structure includes a substrate having thereon a first, a second, and a third OD regions arranged in a row. The first, second, and third OD regions are separated from one another by an isolation region. The isolation region includes a first intervening isolation region between the first OD region and the second OD region, and a second intervening isolation region between the second the third OD region. A first select transistor is formed on the first OD region. A floating gate transistor is formed on the second OD region. The floating gate transistor is serially coupled to the first select transistor. The floating gate transistor includes a floating gate completely overlapped with the second OD region and is partially overlapped with the first and second intervening isolation regions. A second select transistor is on the third OD region and serially coupled to the floating gate transistor.
Abstract translation: 非易失性存储器结构包括其上具有排列成一排的第一，第二和第三OD区域的基板。 第一，第二和第三OD区域通过隔离区域彼此分离。 隔离区域包括在第一OD区域和第二OD区域之间的第一介入隔离区域和第二OD区域之间的第二中间隔离区域。 第一选择晶体管形成在第一OD区上。 在第二OD区域上形成浮栅晶体管。 浮栅晶体管串联耦合到第一选择晶体管。 浮栅晶体管包括与第二OD区完全重叠的浮置栅极，并与第一和第二中间隔离区域部分重叠。 第二选择晶体管位于第三OD区上，并串联耦合到浮栅晶体管。
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公开(公告)号：US11980026B2
公开(公告)日：2024-05-07
申请号：US17839519
申请日：2022-06-14
Applicant: eMemory Technology Inc.
Inventor： Tsung-Mu Lai , Chun-Yuan Lo , Chun-Chieh Chao
CPC classification number: H10B20/20 , G11C7/24 , G11C11/1673 , G11C11/1675 , G11C11/1677 , G11C13/003 , G11C13/0038 , G11C13/004 , G11C13/0064 , H01L23/5256 , G11C2013/0045 , G11C2213/79
Abstract: A random code generating method for the magnetoresistive random access memory is provided. Firstly, a first magnetoresistive random access memory cell and a second magnetoresistive random access memory cell are programmed into an anti-parallel state. Then, an initial value of a control current is set. Then, an enroll action is performed on the first and second magnetoresistive random access memory cells. If the first and second magnetoresistive random access memory cells fail to pass the verification action, the control current is increased by a current increment, and the step of setting the control current is performed again. If the first and second magnetoresistive random access memory cells pass the verification action, a one-bit random code is stored in the first magnetoresistive random access memory cell or the second magnetoresistive random access memory cell.
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Patent Agency Ranking
公开(公告)号：US20220246758A1
公开(公告)日：2022-08-04
申请号：US17721367
申请日：2022-04-15
Applicant: eMemory Technology Inc.
Inventor： Chih-Hsin Chen , Shih-Chen Wang , Tsung-Mu Lai , Wen-Hao Ching , Chun-Yuan Lo , Wei-Chen Chang
Abstract: A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure.
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公开(公告)号：US20170206968A1
公开(公告)日：2017-07-20
申请号：US15352609
申请日：2016-11-16
Applicant: eMemory Technology Inc.
Inventor： Tsung-Mu Lai , Wen-Hao Ching , Chen-Hao Po
IPC: G11C16/12 , H01L27/115 , G11C16/14 , G11C16/08 , G11C16/24
CPC classification number: H01L27/11558 , G11C7/065 , G11C7/10 , G11C7/12 , G11C7/22 , G11C8/10 , G11C16/0408 , G11C16/0433 , G11C16/0458 , G11C16/08 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/16 , G11C16/24 , G11C16/26 , G11C16/30 , H01L23/528 , H01L27/0207 , H01L27/11517 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/1203 , H01L29/0649 , H01L29/0847 , H01L29/1095 , H01L29/42328
Abstract: A memory array includes a plurality of memory pages, each memory page includes a plurality of memory cells, and each memory cell includes a floating gate module, a control element, and an erase element. The floating gate module is disposed in a first well, the erase element is disposed in a second well, and the control element is disposed in a third well. The first well, the second well and the third well are disposed in a deep doped region, and memory cells of the plurality of memory pages are all disposed in the deep doped region. Therefore, the spacing rule between deep doped regions is no longer be used to limit the circuit area of the memory array and the circuit area of the memory array can be reduced.
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公开(公告)号：US20160293261A1
公开(公告)日：2016-10-06
申请号：US15065878
申请日：2016-03-10
Applicant: eMemory Technology Inc.
Inventor： Chih-Hsin Chen , Shih-Chen Wang , Tsung-Mu Lai
CPC classification number: G11C16/14 , G11C16/0441 , G11C16/10 , G11C16/26 , G11C2216/10
Abstract: A memory cell includes a floating gate transistor, a word line transistor, a first capacitance element, and a second capacitance element. The floating gate transistor has a first terminal for receiving a bit line signal, a second terminal, and a floating gate. The word line transistor has a first terminal coupled to the second terminal of the floating gate transistor, a second terminal for receiving a third voltage, and a control terminal for receiving a word line signal. A voltage passing device is for outputting a second voltage during an inhibit operation and a first voltage during a program operation or an erase operation. The first capacitance element is coupled to the first voltage passing device and the floating gate, and for receiving a first control signal. The second capacitance element is for receiving at a second control signal.
Abstract translation: 存储单元包括浮栅晶体管，字线晶体管，第一电容元件和第二电容元件。 浮栅晶体管具有用于接收位线信号的第一端子，第二端子和浮置栅极。 字线晶体管具有耦合到浮置栅极晶体管的第二端子的第一端子，用于接收第三电压的第二端子和用于接收字线信号的控制端子。 电压通过装置用于在禁止操作期间输出第二电压以及在编程操作或擦除操作期间输出第一电压。 第一电容元件耦合到第一电压通过装置和浮动栅极，并用于接收第一控制信号。 第二电容元件用于在第二控制信号处接收。
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公开(公告)号：US20240395342A1
公开(公告)日：2024-11-28
申请号：US18417389
申请日：2024-01-19
Applicant: eMemory Technology Inc.
Inventor： Chia-Jung HSU , Yun-Jen Ting , Cheng-Heng Chung , Chun-Hsiao Li , Tsung-Mu Lai
Abstract: A non-volatile memory cell includes a select transistor and a memory transistor. The first drain/source terminal of the select transistor is connected with a first control terminal. The second drain/source terminal of the select transistor is connected with the first drain/source terminal of the memory transistor. The gate terminal of the select transistor is connected with a select gate terminal. The second drain/source terminal of the memory transistor is connected with a second control terminal. The gate terminal of the memory transistor is connected with a memory gate terminal. During a program action, the select transistor is turned on, and a tapered channel is formed in the memory transistor. The tapered channel is pinched off near the first drain/source terminal of the memory transistor, and plural hot carriers near a pinch off point are injected into the charge storage layer.
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公开(公告)号：US11929434B2
公开(公告)日：2024-03-12
申请号：US17721367
申请日：2022-04-15
Applicant: eMemory Technology Inc.
Inventor： Chih-Hsin Chen , Shih-Chen Wang , Tsung-Mu Lai , Wen-Hao Ching , Chun-Yuan Lo , Wei-Chen Chang
CPC classification number: H01L29/7835 , H01L29/0653 , H01L29/0847 , H01L29/1083
Abstract: A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure.
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