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公开(公告)号：US12224006B2
公开(公告)日：2025-02-11
申请号：US18031356
申请日：2022-07-07
Inventor： Xingsheng Wang , Yinghao Ma , Fan Yang , Chengxu Wang , Menghua Huang , Xiangshui Miao
Abstract: A high-speed and large-current adjustable pulse circuit, an operating circuit and an operating method of a phase-change memory are provided. The high-speed and large-current adjustable pulse circuit is provided with a clamping structure, a current mirror structure and a leakage current shutdown structure. The clamping structure including a clamping operational amplifier and a first MOS transistor is configured to generate a reference current. The current mirror structure is configured to generate an output current proportional to the reference current. The leakage current shutdown structure is configured to turn off the current mirror structure and reduce leakage current when pulse disappear. In this way, a device with an adjustable current and a reduced leakage current is realized.
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公开(公告)号：US12217789B2
公开(公告)日：2025-02-04
申请号：US17844259
申请日：2022-06-20
Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
Inventor： Daoxun Wu , Weibing Shang
IPC: G11C11/00 , G11C11/4091
Abstract: Embodiments of the disclosure provide a control amplification circuit, a sensitive amplifier and a semiconductor memory. The control amplification circuit includes: a power consumption control circuit, configured to receive a power consumption control signal and output a first reference signal according to the power consumption control signal; an isolating circuit, configured to determine a control instruction signal and generate an isolation control signal according to the control instruction signal; and an amplification circuit, configured to receive the first reference signal, the isolation control signal and a signal to be processed, and process the signal to be processed based on the first reference signal and the isolation control signal to obtain a target amplified signal.
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公开(公告)号：US12211553B2
公开(公告)日：2025-01-28
申请号：US17939021
申请日：2022-09-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Won Hee Cho , Ji Sung Byun , Dong Eun Shin
Abstract: A storage system includes a non-volatile memory (NVM) device, having a memory cell array, and a storage controller. The storage controller receives a write command and data from a host and controls the NVM device to write the data in the memory cell array. Additionally, the storage controller determines a memory region of the memory cell array in which the data will be written, clusters a plurality of word lines into a plurality of groups on the basis of feature information of the plurality of word lines, rearranges an access order in units of groups according to the feature information, and accesses the word lines in the rearranged order to write the data in the memory region.
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公开(公告)号：US20250021235A1
公开(公告)日：2025-01-16
申请号：US18794280
申请日：2024-08-05
Applicant: Rambus Inc.
Inventor： Aws Shallal , Micheal Miller , Stephen Horn
IPC: G06F3/06 , G06F11/00 , G06F11/14 , G06F12/0802 , G06F12/14 , G06F13/16 , G11C5/04 , G11C7/10 , G11C11/00 , G11C14/00
Abstract: Disclosed herein are techniques for implementing high-throughput low-latency hybrid memory modules with improved data backup and restore throughput, enhanced non-volatile memory controller (NVC) resource access, and enhanced mode register setting programmability. Embodiments comprise a command replicator to generate sequences of one or more DRAM read and/or write and/or other commands to be executed in response to certain local commands from a non-volatile memory controller (NVC) during data backup and data restore operations. Other embodiments comprise an access engine to enable an NVC in a host control mode to trigger entry into a special mode and issue commands to access a protected register space. Some embodiments comprise a mode register controller to capture and store the data comprising mode register setting commands issued during a host control mode, such that an NVC can program the DRAM mode registers in an NVC control mode.
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5.发明授权公开(公告)号：US12190928B2
公开(公告)日：2025-01-07
申请号：US17970788
申请日：2022-10-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Younghyun Kim , Sechung Oh , Heeju Shin , Jaehoon Kim , Sanghwan Park , Junghwan Park
Abstract: A magnetoresistive random access memory device includes a pinned layer; a tunnel barrier layer on the pinned layer; a free layer structure on the tunnel barrier layer, the free layer structure including a plurality of magnetic layers and a plurality of metal insertion layers between the magnetic layers; and an upper oxide layer on the free layer structure, wherein each of the metal insertion layers includes a non-magnetic metal material doped with a magnetic material, and the metal insertion layers are spaced apart from each other.
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Patent Agency Ranking
公开(公告)号：US12189562B2
公开(公告)日：2025-01-07
申请号：US17846988
申请日：2022-06-22
Applicant: Micron Technology, Inc.
Inventor： Qing Liang , Yang Lu
Abstract: Methods, systems, and devices for memory systems having a selectively interfaceable memory subsystem are described. A memory system may include the memory subsystem that may be configurable to provide volatile storage, nonvolatile storage, or both to a host system. The memory subsystem may include a plurality of ports each capable of communicating with the host system using different interfaces. The memory subsystem may be dynamically configurable to perform different functions based on the demands of the host system. In some examples, memory systems described herein may include a first memory subsystem to provide nonvolatile storage to the host system, a second memory subsystem to provide volatile storage to the host system, and a third memory subsystem configurable to provide volatile storage or nonvolatile storage or both to the host system.
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公开(公告)号：US12182456B2
公开(公告)日：2024-12-31
申请号：US18507598
申请日：2023-11-13
Applicant: Lodestar Licensing Group, LLC
Inventor： Carla L. Christensen , Zahra Hosseinimakarem , Bhumika Chhabra
IPC: G06F3/00 , G06F3/06 , G06F16/535 , G06F16/583 , G06V20/00 , G06V40/10 , G06V40/19 , G11C11/00 , G06V40/16
Abstract: Systems, apparatuses, and methods related to image based media type selection are described. Memory systems can include multiple types of memory media (e.g., volatile and/or non-volatile). Determinations of which memory media types to write image data to can be made and the data can be written (e.g., stored) in the determined type of memory media. A determined memory media type can be based on attributes of the data. In an example, a method can include receiving, by a memory system that comprises a plurality of memory media types, initial image data from an image sensor coupled to the memory system, identifying one or more attributes of the initial image data, determining a type of memory media to write the initial image data to based on the identified attributes of the initial image data, and selecting, based at least in part on the determined type of memory media, a first memory type of the plurality of memory media types to write the initial image data.
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公开(公告)号：US12148471B2
公开(公告)日：2024-11-19
申请号：US17892130
申请日：2022-08-22
Inventor： Yun-Feng Kao , Katherine H Chiang
Abstract: A memory device, an operation method of a memory cell in a memory device and a semiconductor die are provided. A computational memory cell in the memory device includes: a field effect transistor (FET), with a changeable threshold voltage; and resistive storage devices, connected by a common terminal coupled to a source/drain terminal of the FET. By altering the threshold voltage of the FET, a logic function of the computational memory cell can be changed. During a logic operation, inputs are provided to the computational memory cell as resistance states of the resistive storage devices, and a current passing through a conduction channel of the FET is functioned as an output for the logic operation.
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公开(公告)号：US12112797B1
公开(公告)日：2024-10-08
申请号：US18602078
申请日：2024-03-12
Applicant: Shanghai Jiao Tong University
Inventor： Xinfei Guo , Runxi Wang
IPC: G11C11/00 , G06F7/505 , G06F7/544 , G11C11/419
CPC classification number: G11C11/419 , G06F7/505 , G06F7/5443
Abstract: The present disclosure provides a cross-layer reconfigurable static random access memory (SRAM) based compute-in-memory (CIM) macro and method for edge intelligence. The cell includes a SRAM cell and a column-shared reconfigurable Boolean computation cell. A reconfiguration computation is performed based on the SRAM cell to obtain a reconfigured structure; the column-shared reconfigurable Boolean computation cell outputs a computation result based on the reconfigured structure; and a peripheral computation circuit supporting pipelined bit-serial addition outputs an in-memory addition result on a basis of a Boolean computation. In order to meet a requirement of edge artificial intelligence (AI) for a low power consumption and a low hardware overhead, and to enable an accelerator to adapt to a fast iterative software algorithm as much as possible.
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公开(公告)号：US12094545B2
公开(公告)日：2024-09-17
申请号：US18235727
申请日：2023-08-18
Applicant: Intel Corporation
Inventor： Arun Sitaram Athreya , Shankar Natarajan , Sriram Natarajan , Yihua Zhang , Suresh Nagarajan
CPC classification number: G11C16/3427 , G06F3/0604 , G06F3/0659 , G06F3/0688 , G11C11/5642 , G11C11/5671 , G11C16/0483 , G11C16/08 , G11C16/26
Abstract: In one example, reads in a NAND memory device are tracked for sub-groups. When the number of reads to a sub-group meets a threshold, the data at the wordline on which the threshold was met is moved along with the data at neighboring wordlines to an SLC block without moving the entire block. The performance impact and write amplification impact of read disturb mitigation can be significantly reduced while maintaining some data continuity.
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