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    Magnetic Memory Element Including Perpendicular Enhancement Layer and Oxide Cap Layer
    1.
    发明申请
    Magnetic Memory Element Including Perpendicular Enhancement Layer and Oxide Cap Layer 有权

    公开(公告)号：US20250063952A1

    公开(公告)日：2025-02-20

    申请号：US18927997

    申请日：2024-10-26

    Applicant: Avalanche Technology, Inc.

    Inventor： Zihui Wang ,  Yiming Huai

    IPC: H10N50/10 ,  B82Y40/00 ,  G11C11/15 ,  G11C11/16 ,  H01F10/32 ,  H01F41/30 ,  H01L29/66 ,  H10B61/00 ,  H10N50/80 ,  H10N50/85

    Abstract: A magnetic memory element including first and second magnetic free layers having a variable magnetization direction substantially perpendicular to layer planes thereof; a first perpendicular enhancement layer (PEL) interposed between the first and second magnetic free layers; first and second magnetic reference layers having a first invariable magnetization direction substantially perpendicular to layer planes thereof; a second PEL interposed between the first and second magnetic reference layers; an insulating tunnel junction layer formed between the first magnetic free layer and reference layer; an anti-ferromagnetic coupling layer formed adjacent to the second magnetic reference layer; a magnetic fixed layer formed adjacent to the anti-ferromagnetic coupling layer and having a second invariable magnetization direction substantially opposite to the first invariable magnetization direction; and a cap layer formed adjacent to the second magnetic free layer and comprising iron, oxygen, and a metal element.

    MEMORY DEVICE AND OPERATING METHOD THEREOF
    3.
    发明申请
    MEMORY DEVICE AND OPERATING METHOD THEREOF 有权

    公开(公告)号：US20250054530A1

    公开(公告)日：2025-02-13

    申请号：US18399456

    申请日：2023-12-28

    Applicant: SK hynix Inc.

    Inventor： Tae Jung HA

    IPC: G11C11/16

    Abstract: Memory devices and operating methods are disclosed. In an embodiment, a memory device may include a memory cell array including a plurality of memory cells, each of the plurality of memory cells configured to store a data value corresponding to read data to be read out through a plurality of conductive lines, and a read circuit connected to the plurality of conductive to generate the read data corresponding to the data value stored in a selected memory cell among the plurality of memory cells based on or according to whether there is a change in a cell current flowing through the selected memory cell during a single read period.

    Semiconductor storage apparatus
    4.
    发明授权
    Semiconductor storage apparatus 有权

    公开(公告)号：US12223991B2

    公开(公告)日：2025-02-11

    申请号：US17907276

    申请日：2021-04-07

    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION

    Inventor： Taro Tatsuno

    IPC: G11C11/16 ,  H10B61/00

    Abstract: A semiconductor storage apparatus according to one embodiment of the present disclosure includes a plurality of memory cells and a control circuit. Each of the memory cells includes a magnetization reversal memory device and a first switch device that controls a current to flow to the magnetization reversal memory device. The control circuit performs a writing control based on an asymmetric property of a writing error rate curve line with respect to a writing voltage of the magnetization reversal memory device.

    Storage cell and data read/write method and storage array thereof
    5.
    发明授权
    Storage cell and data read/write method and storage array thereof 有权

    公开(公告)号：US12223990B2

    公开(公告)日：2025-02-11

    申请号：US17595459

    申请日：2020-11-11

    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

    Inventor： Xiaoguang Wang ,  Er-Xuan Ping ,  Baolei Wu ,  Yulei Wu

    IPC: G11C11/16 ,  H10B61/00

    Abstract: Embodiments of the present invention provide a storage cell and a data read/write method and storage array thereof. The storage cell includes a bit line, a tunnel junction, and four access transistors. Each access transistor includes at least an active region. The active region includes a source. The sources of the access transistors are all electrically connected to a first end of the tunnel junction. A second end of the tunnel junction is electrically connected to the bit line, and the bit line extends along a first direction. The active regions of the access transistors are isolated from one another. Long-side extension directions of the active regions of the access transistors are the same, and a first angle θ is formed between the long-side extension directions of the active regions and the first direction; wherein θ is a non-right angle.

    MEMORY AND ACCESS METHOD
    6.
    发明申请
    MEMORY AND ACCESS METHOD 有权

    公开(公告)号：US20250046356A1

    公开(公告)日：2025-02-06

    申请号：US18921132

    申请日：2024-10-21

    Applicant: HUAWEI TECHNOLOGIES CO., LTD.

    Inventor： Jeffrey Junhao XU ,  Huan YANG ,  Riqing ZHANG

    IPC: G11C11/16 ,  H10B61/00 ,  H10N50/80 ,  H10N50/85

    Abstract: This application provides a magneto-resistive random access memory, to reduce a chip area. The magneto-resistive random access memory includes: a plurality of stacked stacking layers, where each stacking layer includes a plurality of magnetic memory cells arranged in a two-dimensional manner; and a plurality of selective metal layers, where each stacking layer is disposed between two selective metal layers and is adjacent to the two selective metal layers, and each selective metal layer is connected to a magnetic memory cell in an adjacent stacking layer, and is configured to perform a read/write operation on the magnetic memory cell.

    Memory device with source line control
    7.
    发明授权
    Memory device with source line control 有权

    公开(公告)号：US12217822B2

    公开(公告)日：2025-02-04

    申请号：US18232542

    申请日：2023-08-10

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Perng-Fei Yuh ,  Yih Wang

    IPC: G11C7/10 ,  G11C7/12 ,  G11C8/08 ,  G11C11/16 ,  G11C11/407 ,  G11C17/18

    Abstract: Disclosed herein are related to a memory device including a set of memory cells and a memory controller. In one aspect, each of the set of memory cells includes a select transistor and a storage element connected in series between a corresponding bit line and a corresponding source line. In one aspect, the memory controller is configured to apply a first write voltage to a bit line coupled to a selected memory cell, apply a second write voltage to a word line coupled to a gate electrode of a select transistor of the selected memory cell during a first time period, and apply a third write voltage to a source line coupled to the selected memory cell. The second write voltage may be between the first write voltage and the third write voltage.

    Memory sense amplifier trimming
    8.
    发明授权
    Memory sense amplifier trimming 有权

    公开(公告)号：US12211579B2

    公开(公告)日：2025-01-28

    申请号：US18424164

    申请日：2024-01-26

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Yi-Chun Shih ,  Chia-Fu Lee ,  Yu-Der Chih

    IPC: G11C7/08 ,  G11C7/06 ,  G11C7/10 ,  G11C11/16 ,  G11C29/42

    Abstract: A memory device, such as an MRAM memory, includes a memory array with a plurality of bit cells. The memory array is configured to store trimming information and store user data. A sense amplifier is configured to read the trimming information from the memory array, and a trimming register is configured to receive the trimming information from the sense amplifier. The sense amplifier is configured to receive the trimming information from the trimming register so as to operate in a trimmed mode for reading the user data from the memory array.

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