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公开(公告)号：US20240407159A1
公开(公告)日：2024-12-05
申请号：US18326228
申请日：2023-05-31
Inventor： Yu-Der Chih , Ya-Chin King , Chrong Lin , Jonathan Tsung-Yung Chang , Yun-Sheng Chen , May-Be Chen , Hsin-Yuan Yu
IPC: H10B20/25
Abstract: A memory device is disclosed. The memory device includes a memory cell comprising: a transistor; and a plurality of pairs of resistors coupled to the transistor in series, each of the pairs of resistors including a first resistor and a second resistor. The transistor is formed along a major surface of a substrate. At least a first one of the pairs of resistors are formed in a first one of a plurality of metallization layers disposed above the transistor. At least a second one of the pairs of resistors are formed in a second one of the plurality of metallization layers, the second metallization layer being disposed above the first metallization layer.
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公开(公告)号：US20240347090A1
公开(公告)日：2024-10-17
申请号：US18635929
申请日：2024-04-15
Inventor： Chia-Fu Lee , Hon-Jarn Lin , Po-Hao Lee , Ku-Feng Lin , Yi-Chun Shih , Yu-Der Chih
CPC classification number: G11C11/1675 , G11C11/161 , G11C11/1655 , G11C11/1657 , G11C11/1673 , H10B61/22 , H10N50/10
Abstract: A reference circuit for generating a reference current includes a plurality of resistive elements including at least one magnetic tunnel junction (MTJ). A control circuit is coupled to a first terminal of the at least one MTJ and is configured to selectively flow current through the at least one MTJ in the forward and inverse direction to generate a reference current.
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公开(公告)号：US11984162B2
公开(公告)日：2024-05-14
申请号：US17981977
申请日：2022-11-07
Inventor： Zheng-Jun Lin , Chung-Cheng Chou , Yu-Der Chih , Pei-Ling Tseng
CPC classification number: G11C13/0064 , G11C13/003 , G11C13/004
Abstract: The disclosed invention presents a self-tracking reference circuit that compensates for IR drops and achieves the target resistance state at different temperatures after write operations. The disclosed self-tracking reference circuit includes a replica access path, a configurable resistor network, a replica selector mini-array and a step current generator that track PVT variations to provide a PVT tracking level for RRAM verify operation.
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公开(公告)号：US20240036597A1
公开(公告)日：2024-02-01
申请号：US17877115
申请日：2022-07-29
Inventor： Zheng-Jun Lin , Chung-Cheng Chou , Yu-Der Chih , Chin-I Su
Abstract: A voltage regulator circuit is provided. The voltage regulator circuit includes a voltage regulator configured to provide an output voltage at an output terminal. A plurality of macros are connectable at a plurality of connection nodes of a connector connected to the output terminal of the voltage regulator. A feedback circuit having a plurality of feedback loops is connectable to the plurality of connection nodes. The feedback loop of the plurality of feedback loops, when connected to a connection node of the plurality of connection nodes, is configured to provide an instantaneous voltage of the connection node as a feedback to the voltage regulator. The voltage regulator is configured, in response to the instantaneous voltage, regulate the output voltage to maintain the instantaneous voltage of the connection node approximately equal to a reference voltage.
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公开(公告)号：US11791006B2
公开(公告)日：2023-10-17
申请号：US17816118
申请日：2022-07-29
Inventor： Gu-Huan Li , Chen-Ming Hung , Yu-Der Chih
IPC: G11C17/18 , G11C17/16 , G11C8/10 , G11C7/10 , G11C11/4074 , G11C11/4096 , G11C11/4099
CPC classification number: G11C17/18 , G11C7/1069 , G11C7/1096 , G11C8/10 , G11C11/4074 , G11C11/4096 , G11C11/4099 , G11C17/16
Abstract: A memory circuit includes a bank of non-volatile memory (NVM) devices, a plurality of high-voltage (HV) drivers, a global HV power switch configured to generate a HV power signal, and a plurality of HV power switches coupled to the global HV switch. A first HV power switch of the plurality of HV power switches is coupled to each HV driver of the plurality of HV drivers, the first HV power switch of the plurality of HV power switches is configured to output a power signal responsive to the HV power signal, and each HV driver of the plurality of HV drivers is configured to output a HV activation signal to a corresponding column of the bank of NVM devices responsive to the power signal.
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公开(公告)号：US20230317159A1
公开(公告)日：2023-10-05
申请号：US17709662
申请日：2022-03-31
Inventor： Yu-Der Chih , Chung-Cheng Chou , Chun-Yun Wu , Chen-Ming Hung
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C13/0064 , G11C13/004 , G11C13/0028 , G11C13/0026 , G11C13/0038
Abstract: A memory device includes a main array comprising main memory cells; a redundancy array comprising redundancy memory cells; and write circuitry configured to perform a first programming operation on a main memory cell, to detect whether a current of the main memory cell exceeds a predefined current threshold during the first programming operation, and to disable a second programming operation for a redundancy memory cell if the current of the main memory cell exceeds the predefined current threshold during the first programming operation.
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公开(公告)号：US11735263B2
公开(公告)日：2023-08-22
申请号：US17871144
申请日：2022-07-22
Inventor： Chin-I Su , Chung-Cheng Chou , Yu-Der Chih , Zheng-Jun Lin
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C13/0028 , G11C13/0038 , G11C2013/0078 , G11C2213/79
Abstract: A method of operating a memory circuit includes generating a first voltage by a first amplifier circuit of a first driver circuit coupled to a first column of memory cells, and generating a first current in response to the first voltage. The first current includes a first set of leakage currents and a first write current. The method further includes generating, by a tracking circuit, a second set of leakage currents configured to track the first set of leakage currents of the first column of memory cells, and mirroring the first current in a first path with a second current in a second path by a first current mirror. The second current includes the second set of leakage currents and a second write current. The first write current corresponds to the second write current. The first set of leakage currents corresponds to the second set of leakage currents.
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公开(公告)号：US20230197122A1
公开(公告)日：2023-06-22
申请号：US18168226
申请日：2023-02-13
Inventor： Yi-Chun Shih , Chia-Fu Lee , Yu-Der Chih
CPC classification number: G11C7/08 , G11C7/067 , G11C7/1039 , G11C11/1673 , G11C29/42
Abstract: A memory device, such as an MRAM memory, includes a memory array with a plurality of bit cells. The memory array is configured to store trimming information and store user data. A sense amplifier is configured to read the trimming information from the memory array, and a trimming register is configured to receive the trimming information from the sense amplifier. The sense amplifier is configured to receive the trimming information from the trimming register so as to operate in a trimmed mode for reading the user data from the memory array.
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公开(公告)号：US20230133360A1
公开(公告)日：2023-05-04
申请号：US17825036
申请日：2022-05-26
Inventor： Rawan Naous , Kerem Akarvardar , Mahmut Sinangil , Yu-Der Chih , Saman Adham , Nail Etkin Can Akkaya , Hidehiro Fujiwara , Yih Wang , Jonathan Tsung-Yung Chang
Abstract: Systems and methods for floating-point processors and methods for operating floating-point processors are provided. A floating-point processor includes a quantizer, a compute-in-memory device, and a decoder. The floating-processor is configured to receive an input array in which the values of the input array are represented in floating-point format. The floating-point processor may be configured to convert the floating-point numbers into integer format so that multiply-accumulate operations can be performed on the numbers. The multiply-accumulate operations generate partial sums, which are in integer format. The partial sums can be accumulated until a full sum is achieved, wherein the full sum can then be converted to floating-point format.
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公开(公告)号：US11641193B2
公开(公告)日：2023-05-02
申请号：US17815322
申请日：2022-07-27
Inventor： Chia-Fu Lee , Hon-Jarn Lin , Yu-Der Chih
IPC: H03K3/356
Abstract: A circuit includes cross coupled invertors including a first invertor and a second inventor. The first invertor and the second invertor are cross coupled at a first data node and a second data node. An input unit is coupled between the cross-coupled invertors and a power node. The input unit controls the cross-coupled invertors in response to a first input signal received at a first input terminal of the input unit and a second input signal received at a second input terminal of the input unit. A first transistor is connected between the power node and a supply node. The first transistor connects the power node to the supply node in response to an enable signal changing to a first value. A second transistor is connected between the power node and ground. The second transistor connects the power node to the ground in response to the enable signal changing to a second value.
