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公开(公告)号：US20240365677A1
公开(公告)日：2024-10-31
申请号：US18329588
申请日：2023-06-06
发明人： Jia-Rong Wu , Yi-An Shih , Hsiu-Hao Hu , I-Fan Chang , Rai-Min Huang , Po Kai Hsu
摘要： Provided is a semiconductor device including a substrate, a first interconnection structure, and an MTJ device. The first interconnection structure is disposed on the substrate. The MTJ device is reversely bonded to the first interconnection structure. The MTJ device includes a first electrode layer, a second electrode layer and an MTJ stack structure. The first electrode layer is bonded to the first interconnect structure. The second electrode layer is located above the first electrode layer. The MTJ stack structure is located between the first and second electrode layers. The MTJ stack structure includes a first barrier layer, a free layer and a reference layer. The first barrier layer is located between the first and second electrode layers. The free layer is located between the first barrier layer and the first electrode layer. The reference layer is located between the first barrier layer and the second electrode layer.
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公开(公告)号：US20240363430A1
公开(公告)日：2024-10-31
申请号：US18203654
申请日：2023-05-31
发明人： Chih-Yi Wang , Wei-Che Chen , Hung-Chun Lee , Yun-Yang He , Wei-Hao Chang , Chang-Yih Chen , Kun-Szu Tseng , Yao-Jhan Wang , Ying-Hsien Chen
IPC分类号： H01L21/8234 , H01L27/088 , H01L29/06 , H01L29/66 , H01L29/78
CPC分类号： H01L21/823481 , H01L21/823431 , H01L27/0886 , H01L29/0607 , H01L29/66795 , H01L29/7851 , H01L29/66545
摘要： A method for fabricating a semiconductor device includes the steps of first providing a substrate having an active region as the substrate includes a medium-voltage (MV) region and a low-voltage (LV) region, forming a first divot adjacent to one side of the active region, forming a second divot adjacent to another side of the active region, forming a first liner in the first divot and the second divot and on the substrate of the MV region and LV region, forming a second liner on the first liner, and then removing the second liner, the first liner, and the substrate on the LV region for forming a fin-shaped structure.
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公开(公告)号：US12133474B2
公开(公告)日：2024-10-29
申请号：US18373295
申请日：2023-09-27
发明人： Hui-Lin Wang , Chen-Yi Weng , Chin-Yang Hsieh , Yi-Hui Lee , Ying-Cheng Liu , Yi-An Shih , Jing-Yin Jhang , I-Ming Tseng , Yu-Ping Wang , Chien-Ting Lin , Kun-Chen Ho , Yi-Syun Chou , Chang-Min Li , Yi-Wei Tseng , Yu-Tsung Lai , Jun Xie
摘要： A method of fabricating magnetoresistive random access memory, including providing a substrate, forming a bottom electrode layer, a magnetic tunnel junction stack, a top electrode layer and a hard mask layer sequentially on the substrate, wherein a material of the top electrode layer is titanium nitride, a material of the hard mask layer is tantalum or tantalum nitride, and a percentage of nitrogen in the titanium nitride gradually decreases from a top surface of top electrode layer to a bottom surface of top electrode layer, and patterning the bottom electrode layer, the magnetic tunnel junction stack, the top electrode layer and the hard mask layer into multiple magnetoresistive random access memory cells.
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公开(公告)号：US12132106B2
公开(公告)日：2024-10-29
申请号：US17688821
申请日：2022-03-07
发明人： Shin-Hung Li
IPC分类号： H01L31/109 , H01L29/08 , H01L29/423 , H01L29/78 , H01L31/0328 , H01L31/072
CPC分类号： H01L29/7827 , H01L29/0847 , H01L29/42392
摘要： A semiconductor device and method of fabricating the same, the semiconductor device includes a substrate, a first transistor and a second transistor. The substrate includes a high-voltage region and a low-voltage region. The first transistor is disposed on the HV region, and includes a first gate dielectric layer disposed on a first base, and a first gate electrode on the first gate dielectric layer. The first gate dielectric layer includes a composite structure having a first dielectric layer and a second dielectric layer stacked sequentially. The second transistor is disposed on the LV region, and includes a fin shaped structure protruded from a second base on the substrate, and a second gate electrode disposed on the fin shaped structure. The first dielectric layer covers sidewalls of the second gate electrode and a top surface of the first dielectric layer is even with a top surface of the second gate electrode.
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公开(公告)号：US20240355920A1
公开(公告)日：2024-10-24
申请号：US18761282
申请日：2024-07-01
发明人： Po-Yu Yang , Hsun-Wen Wang
IPC分类号： H01L29/778 , H01L29/06 , H01L29/66
CPC分类号： H01L29/7786 , H01L29/0649 , H01L29/66462 , H01L29/6656
摘要： A high electron mobility transistor includes an epitaxial stack on a substrate, a gate structure on the epitaxial stack, a passivation layer on the epitaxial stack and the gate structure, and an air gap between the passivation layer and the gate structure. The gate structure includes a semiconductor gate layer and a metal gate layer on the semiconductor gate layer. The air gap is in direct contact with a sidewall of the passivation layer, a sidewall of the metal gate layer, a sidewall and a top surface of the semiconductor gate layer.
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公开(公告)号：US20240355894A1
公开(公告)日：2024-10-24
申请号：US18757573
申请日：2024-06-28
发明人： Ming-Hua Tsai , Jung Han , Ming-Chi Li , Chih-Mou Lin , Yu-Hsiang Hung , Yu-Hsiang Lin , Tzu-Lang Shih
IPC分类号： H01L29/423 , H01L29/06 , H01L29/08 , H01L29/66 , H01L29/78
CPC分类号： H01L29/42368 , H01L29/0607 , H01L29/0847 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device includes a semiconductor substrate, a first gate oxide layer, and a first source/drain doped region. The first gate oxide layer is disposed on the semiconductor substrate, and the first gate oxide layer includes a main portion and an edge portion having a sloping sidewall. The first source/drain doped region is disposed in the semiconductor substrate and located adjacent to the edge portion of the first gate oxide layer. The first source/drain doped region includes a first portion and a second portion. The first portion is disposed under the edge portion of the first gate oxide layer in a vertical direction, and the second portion is connected with the first portion.
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公开(公告)号：US20240347621A1
公开(公告)日：2024-10-17
申请号：US18755727
申请日：2024-06-27
发明人： Chih-Tung Yeh , Ming-Chang Lu
IPC分类号： H01L29/66 , H01L29/20 , H01L29/778
CPC分类号： H01L29/66462 , H01L29/2003 , H01L29/778
摘要： A high electron mobility transistor includes a substrate. A first III-V compound layer is disposed on the substrate. A second III-V compound layer is embedded within the first III-V compound layer. A P-type gallium nitride gate is embedded within the second Ill-V compound layer. A gate electrode is disposed on the second III-V compound layer and contacts the P-type gallium nitride gate. A source electrode is disposed at one side of the gate electrode. A drain electrode is disposed at another side of the gate electrode.
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公开(公告)号：US20240347108A1
公开(公告)日：2024-10-17
申请号：US18201213
申请日：2023-05-24
发明人： Chi-Hsiu HSU , Yu-Huan YEH , Cheng-Hsiao LAI , Guan-Lin CHEN , Chuan-Fu WANG , Hung-Yu FAN CHIANG
IPC分类号： G11C13/00
CPC分类号： G11C13/0064
摘要： A forming method of a ReRAM array includes steps as follows: Firstly, a first pulse is applied to a first ReRAM unit in the ReRAM array. Afterwards, a second pulse is applied to the first ReRAM unit, wherein the electrical property of the first pulse is opposite to that of the second pulse. Then, a verification pulse is applied to the first ReRAM unit to verify whether the first resistance value of the first ReRAM unit passes a preset threshold. When the first resistance value passes the preset threshold value, a third pulse is applied to the first ReRAM unit, wherein the first pulse and the third pulse have the same electrical property, and the first pulse has a voltage value substantially the same to that of the third pulse.
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公开(公告)号：US20240339534A1
公开(公告)日：2024-10-10
申请号：US18746063
申请日：2024-06-18
发明人： Che-Hua Chang , Shin-Hung Li , Tsung-Yu Yang , Ruei-Jhe Tsao
IPC分类号： H01L29/78 , H01L29/10 , H01L29/40 , H01L29/423 , H01L29/66
CPC分类号： H01L29/7825 , H01L29/1095 , H01L29/401 , H01L29/42368 , H01L29/66704
摘要： A semiconductor device includes a semiconductor substrate, a trench, and a gate structure. The trench is disposed in the semiconductor substrate. The gate structure is disposed on the semiconductor substrate. The gate structure includes a gate electrode, a first gate oxide layer, and a second gate oxide layer. A first portion of the gate electrode is disposed in the trench, and a second portion of the gate electrode is disposed outside the trench. The first gate oxide layer is disposed between the gate electrode and the semiconductor substrate. At least a portion of the first gate oxide layer is disposed in the trench. The second gate oxide layer is disposed between the second portion of the gate electrode and the semiconductor substrate in a vertical direction. A thickness of the second gate oxide layer is greater than a thickness of the first gate oxide layer.
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公开(公告)号：US20240339501A1
公开(公告)日：2024-10-10
申请号：US18143095
申请日：2023-05-04
发明人： Che-Hsien Lin , Te-Chang Hsu , Chun-Jen Huang , Chun-Chia Chen
CPC分类号： H01L29/0847 , H01L29/66795 , H01L29/7851
摘要： A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming a fin-shaped structure on the substrate, forming a gate structure on the fin-shaped structure, removing the fin-shaped structure to form a recess, forming a first epitaxial layer in the recess adjacent to the gate structure, and then forming a second epitaxial layer on the first epitaxial layer. Preferably, the semiconductor device further includes a first protrusion on one side of the first epitaxial layer and a second protrusion on another side of the first epitaxial layer.
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