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公开(公告)号:US20240363430A1
公开(公告)日:2024-10-31
申请号:US18203654
申请日:2023-05-31
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Chih-Yi Wang , Wei-Che Chen , Hung-Chun Lee , Yun-Yang He , Wei-Hao Chang , Chang-Yih Chen , Kun-Szu Tseng , Yao-Jhan Wang , Ying-Hsien Chen
IPC: H01L21/8234 , H01L27/088 , H01L29/06 , H01L29/66 , H01L29/78
CPC classification number: H01L21/823481 , H01L21/823431 , H01L27/0886 , H01L29/0607 , H01L29/66795 , H01L29/7851 , H01L29/66545
Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having an active region as the substrate includes a medium-voltage (MV) region and a low-voltage (LV) region, forming a first divot adjacent to one side of the active region, forming a second divot adjacent to another side of the active region, forming a first liner in the first divot and the second divot and on the substrate of the MV region and LV region, forming a second liner on the first liner, and then removing the second liner, the first liner, and the substrate on the LV region for forming a fin-shaped structure.
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公开(公告)号:US20240379670A1
公开(公告)日:2024-11-14
申请号:US18206609
申请日:2023-06-06
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Ya-Ting Hu , Chih-Yi Wang , Yao-Jhan Wang , Wei-Che Chen , Kun-Szu Tseng , Yun-Yang He , Wen-Liang Huang , Lung-En Kuo , Po-Tsang Chen , Po-Chang Lin , Ying-Hsien Chen
IPC: H01L27/088 , H01L21/762
Abstract: A semiconductor device includes a substrate with a high voltage region and a low voltage region. A first deep trench isolation is disposed within the high voltage region. The first deep trench isolation includes a first deep trench and a first insulating layer filling the first deep trench. The first deep trench includes a first sidewall and a second sidewall facing the first sidewall. The first sidewall is formed by a first plane and a second plane. The edge of the first plane connects to the edge of the second plane. The slope of the first plane is different from the slope of the second plane.
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