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公开(公告)号：US20240365676A1
公开(公告)日：2024-10-31
申请号：US18770678
申请日：2024-07-12
发明人： YA-LING LEE , TSANN LIN , HAN-JONG CHIA
CPC分类号： H10N50/10 , G01R33/093 , G01R33/098 , G11C11/161 , H10B61/00 , H10N50/01 , H10N50/80 , H10N50/85
摘要： A magnetic tunnel junction (MTJ) element is provided. The MTJ element includes a hard bias layer, a reference layer disposed over the hard bias layer, a tunnel barrier layer disposed over the reference layer, a free layer disposed over the tunnel barrier layer, and a diffusion barrier layer disposed over the free layer wherein the diffusion barrier layer comprises an amorphous and nonmagnetic film of a form X-Z, where X is Fe or Co and Z is Hf, Y, or Zr. The MTJ element in accordance with the present disclosure exhibits a low resistance desired for a low-power write operation, and a high TMR coefficient desired for a low bit-error-rate (BER) read operation.
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公开(公告)号：US20240357943A1
公开(公告)日：2024-10-24
申请号：US18760005
申请日：2024-06-30
发明人： Chiu-Jung Chiu , Ya-Sheng Feng , I-Ming Tseng , Yi-An Shih , Yu-Chun Chen , Yi-Hui Lee , Chung-Liang Chu , Hsiu-Hao Hu
摘要： A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.
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公开(公告)号：US12127483B2
公开(公告)日：2024-10-22
申请号：US17388484
申请日：2021-07-29
发明人： Bi-Shen Lee , Hai-Dang Trinh , Hsun-Chung Kuang , Cheng-Yuan Tsai
摘要： Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a memory cell with a sidewall spacer, and/or an etch stop layer, doped to reduce charge accumulation at an interface between the sidewall spacer and the etch stop layer. The memory cell comprises a bottom electrode, a data storage element overlying the bottom electrode, and a top electrode overlying the data storage element. The sidewall spacer overlies the bottom electrode on a common sidewall formed by the data storage element and the top electrode, and the etch stop layer lines the sidewall spacer. The sidewall spacer and the etch stop layer directly contact at the interface and form an electric dipole at the interface. The doping to reduce charge accumulation reduces an electric field produced by the electric dipole, thereby reducing the effect of the electric field on the memory cell.
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公开(公告)号：US12127482B2
公开(公告)日：2024-10-22
申请号：US17247365
申请日：2020-12-09
CPC分类号： H10N50/10 , G11C11/161 , H10B61/00 , H10N50/85 , H10N52/80
摘要： A spin-orbit torque (SOT)-MRAM comprising a first magnetic tunneling junction (MTJ) having a first distance and having a first critical voltage. A second MTJ having a second distance and having a second critical voltage, wherein the first distance and the second distance are different, wherein the first critical voltage and the second critical voltages are different. A metal rail in direct contact with the first MTJ and the second MTJ, wherein the metal rail injects a spin current in to both the first MTJ and the second MTJ.
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公开(公告)号：US20240349622A1
公开(公告)日：2024-10-17
申请号：US18218926
申请日：2023-07-06
发明人： Jaewoo Jeong , Tiar Ikhtiar , Panagiotis Charilaos Filippou , Chirag Garg , Mahesh Govind Samant
摘要： A magnetic memory device includes a substrate, a seed layer above the substrate, a chemical templating layer above the seed layer, and a first magnetic layer above the chemical templating layer. The seed layer includes ScxN, MnxN, or MgO substantially oriented in (001) direction. The chemical templating layer includes a binary alloy having a Cu3Au prototype structure or a BiF3 prototype structure. The first magnetic layer includes a Heusler compound having perpendicular magnetic anisotropy.
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公开(公告)号：US12119036B2
公开(公告)日：2024-10-15
申请号：US18096089
申请日：2023-01-12
CPC分类号： G11C11/1673 , G11C11/1675 , H10B61/00 , H10N50/80
摘要： A magnetic memory device may include a magnetic track, which is extended in a first direction, and a first electrode, which is provided at a biasing point of the magnetic track and is configured to apply a voltage to the magnetic track. The magnetic track includes a first region between a first end of the magnetic track and the biasing point and a second region between the biasing point and a second end of the magnetic track. The first electrode may be configured to cause a difference between a current density in the first region and a current density in the second region.
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公开(公告)号：US20240341200A1
公开(公告)日：2024-10-10
申请号：US18748476
申请日：2024-06-20
发明人： Wei-Jen CHEN , Ya-Jui TSOU , Chee-Wee LIU , Shao-Yu LIN , Chih-Lin WANG
摘要： A memory structure comprises a dielectric layer, a first ferromagnetic bottom electrode, a second ferromagnetic bottom electrode, an SOT channel layer, and an MTJ structure. The dielectric layer is over the substrate. The first ferromagnetic bottom electrode extends through the dielectric layer. The second ferromagnetic bottom electrode extends through the dielectric layer, and is spaced apart from the first ferromagnetic bottom electrode. The SOT channel layer extends from the first ferromagnetic bottom electrode to the second ferromagnetic bottom electrode. The MTJ structure is over the SOT channel layer.
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公开(公告)号：US20240339417A1
公开(公告)日：2024-10-10
申请号：US18295518
申请日：2023-04-04
IPC分类号： H01L23/552 , H01L25/065 , H10B61/00 , H10B80/00 , H10N50/10
CPC分类号： H01L23/552 , H01L25/0655 , H10B61/00 , H10B80/00 , H10N50/10 , G11C11/1673 , G11C11/1675
摘要： An example apparatus includes a magnetic device, top magnetic shielding, bottom magnetic shielding, and a plurality of side magnetic shielding elements. The top magnetic shielding includes a first magnetic material. The bottom magnetic shielding includes a second magnetic material. Each side magnetic shielding element of the plurality of side magnetic shielding elements includes a third magnetic material. Each one of the plurality of side magnetic shielding elements extend at least partially between the top surface of the magnetic device and the bottom surface of the magnetic device. The plurality of side magnetic shielding elements only partially extends over a first side surface.
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公开(公告)号：US12112784B2
公开(公告)日：2024-10-08
申请号：US17751898
申请日：2022-05-24
发明人： Sungchul Lee , Kyungjin Lee
CPC分类号： G11C11/161 , H10B61/00 , H10N50/10 , H10N50/80 , H10N50/85
摘要： A magneto resistive random access memory (MRAM) device including a spin orbit torque structure including a stack of an oxide layer pattern, a ferromagnetic pattern, and a non-magnetic pattern; and a magnetic tunnel junction (MTJ) structure on the spin orbit torque structure, the MTJ structure including a stack of a free layer pattern, a tunnel barrier pattern, and a pinned layer pattern, wherein the spin orbit torque structure extends in a first direction parallel to an upper surface of the spin orbit torque structure, the ferromagnetic pattern includes a horizontal magnetic material, and the free layer pattern has a magnetization direction in a vertical direction perpendicular to the upper surface of the spin orbit torque structure, the magnetization direction being changeable in response to spin currents generated in the spin orbit torque structure.
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公开(公告)号：US12108685B2
公开(公告)日：2024-10-01
申请号：US17479668
申请日：2021-09-20
摘要： A semiconductor structure comprises a reference layer of a magnetic random-access memory pillar structure, the reference layer having a first diameter, a free layer of the magnetic random-access memory pillar structure disposed over the reference layer, the free layer having a second diameter, and an electrode layer of the magnetic random-access memory pillar structure disposed over the free layer, the electrode layer having a third diameter. At least two of the first diameter, the second diameter and the third diameter are different.
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