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公开(公告)号：US20240365676A1
公开(公告)日：2024-10-31
申请号：US18770678
申请日：2024-07-12
发明人： YA-LING LEE , TSANN LIN , HAN-JONG CHIA
CPC分类号： H10N50/10 , G01R33/093 , G01R33/098 , G11C11/161 , H10B61/00 , H10N50/01 , H10N50/80 , H10N50/85
摘要： A magnetic tunnel junction (MTJ) element is provided. The MTJ element includes a hard bias layer, a reference layer disposed over the hard bias layer, a tunnel barrier layer disposed over the reference layer, a free layer disposed over the tunnel barrier layer, and a diffusion barrier layer disposed over the free layer wherein the diffusion barrier layer comprises an amorphous and nonmagnetic film of a form X-Z, where X is Fe or Co and Z is Hf, Y, or Zr. The MTJ element in accordance with the present disclosure exhibits a low resistance desired for a low-power write operation, and a high TMR coefficient desired for a low bit-error-rate (BER) read operation.
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公开(公告)号：US20240365564A1
公开(公告)日：2024-10-31
申请号：US18768995
申请日：2024-07-10
发明人： Chih-Fan Huang , Wen-Chiung Tu , Liang-Wei Wang , Dian-Hau Chen , Yen-Ming Chen
摘要： Semiconductor device and methods of forming the same are provided. A semiconductor device according to one embodiment includes a first source/drain feature and a second source/drain feature, a first metal line disposed in a first dielectric layer and electrically connected to the first source/drain feature, a second metal line disposed in the first dielectric layer and electrically connected to the second source/drain feature, and a first memory element disposed over the first dielectric layer and electrically connected to the first source/drain feature by way of the first metal line. A width of the first metal line is different from a width of the second metal line. By changing the widths of the first metal line and the second metal line, a source line series resistance of a semiconductor device can be advantageously reduced without changing a pitch of two metal lines.
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公开(公告)号：US20240365542A1
公开(公告)日：2024-10-31
申请号：US18764868
申请日：2024-07-05
发明人： Wei-Cheng WU , Li-Feng TENG
IPC分类号： H10B41/42 , H01L21/28 , H01L29/423 , H01L29/66 , H10B41/30 , H10B41/35 , H10B41/44 , H10B41/47 , H10B41/48 , H10B43/30
CPC分类号： H10B41/42 , H01L29/40114 , H01L29/42328 , H01L29/42344 , H01L29/66545 , H10B41/30 , H10B41/35 , H10B41/44 , H10B41/47 , H10B41/48 , H10B43/30
摘要： A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer, and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.
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公开(公告)号：US20240364317A1
公开(公告)日：2024-10-31
申请号：US18768843
申请日：2024-07-10
发明人： Yung-Chen CHIEN , Xiangdong CHEN , Hui-Zhong ZHUANG , Tzu-Ying LIN , Jerry Chang Jui KAO , Lee-Chung LU
IPC分类号： H03K3/3562 , H03K3/012 , H03K3/037
CPC分类号： H03K3/35625 , H03K3/012 , H03K3/0372 , H03K3/0375
摘要： A flip-flop circuit includes a first inverter configured to receive a first clock signal and output a second clock signal, a second inverter configured to receive the second clock signal and output a third clock signal, a master latch including a transmission circuit, and a slave latch including a first feedback inverter. The first feedback inverter includes a first transistor configured to receive the first clock signal and a second transistor configured to receive the second clock signal, and the transmission circuit includes a third transistor configured to receive the third clock signal.
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公开(公告)号：US20240363756A1
公开(公告)日：2024-10-31
申请号：US18737644
申请日：2024-06-07
发明人： Yu-Lien Huang , Yi-Shan Chen , Kuan-Da Huang , Han-Yu Lin , Li-Te Lin , Ming-Huan Tsai
IPC分类号： H01L29/78 , H01L29/40 , H01L29/417
CPC分类号： H01L29/785 , H01L29/401 , H01L29/41791
摘要： A semiconductor device includes: a semiconductor fin extending along a first lateral direction; a gate structure extending along a second lateral direction perpendicular to the first lateral direction and straddling the semiconductor fin; an epitaxial structure disposed in the semiconductor fin and next to the gate structure; a first interconnect structure extending along the second lateral direction and disposed above the epitaxial structure; and a dielectric layer including a first portion and a second portion that form a stair.
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公开(公告)号：US20240363732A1
公开(公告)日：2024-10-31
申请号：US18769168
申请日：2024-07-10
发明人： Mao-Lin HUANG , Lung-Kun CHU , Chung-Wei HSU , Jia-Ni YU , Chun-Fu LU , Kuo-Cheng CHIANG , Kuan-Lun CHENG , Chih-Hao WANG
IPC分类号： H01L29/66 , H01L21/8234 , H01L29/06 , H01L29/78
CPC分类号： H01L29/66795 , H01L21/823431 , H01L29/0673 , H01L29/7851
摘要： A semiconductor device structure is provided. The semiconductor device structure includes a gate structure formed over nanostructures. The gate structure includes a gate dielectric layer, and a fill layer over the gate dielectric layer. The semiconductor device structure includes a protection layer formed over the fill layer, and a gate spacer layer formed adjacent to the gate structure. The semiconductor device structure includes an insulating layer formed over the protection layer, and the insulating layer is in direct contact with the gate spacer layer.
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公开(公告)号：US20240363714A1
公开(公告)日：2024-10-31
申请号：US18767188
申请日：2024-07-09
发明人： Kuan-Hao CHENG , Wei-Yang LEE , Tzu-Hua CHIU , Wei-Han FAN , Po-Yu LIN , Chia-Pin LIN
IPC分类号： H01L29/423 , H01L29/06 , H01L29/66 , H01L29/786
CPC分类号： H01L29/42392 , H01L29/0673 , H01L29/66545 , H01L29/66636 , H01L29/66787 , H01L29/78618 , H01L29/78696
摘要： A semiconductor structure is provided. The semiconductor structure includes a first nanostructure stacked over and spaced apart from a second nanostructure, a gate stack wrapping around the first nanostructure and the second nanostructure, a source/drain feature adjoining the first nanostructure and the second nanostructure, and a first inner spacer layer interposing the gate stack and the source/drain feature and interposing the first nanostructure and the second nanostructure. A dopant in the source/drain feature has a first concentration at an interface between the first inner spacer layer and the source/drain feature and a second concentration at a first distance away from the interface. The first concentration is higher than the second concentration.
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公开(公告)号：US20240363703A1
公开(公告)日：2024-10-31
申请号：US18771434
申请日：2024-07-12
发明人： Jung-Hung CHANG , Lo Heng CHANG , Zhi-Chang LIN , Shih-Cheng CHEN , Chien-Ning YAO , Kuo-Cheng CHIANG , Chih-Hao WANG
IPC分类号： H01L29/417 , H01L21/8234 , H01L29/06 , H01L29/40 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786
CPC分类号： H01L29/41733 , H01L21/823475 , H01L29/401 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/66742 , H01L29/775 , H01L29/78606 , H01L29/0653 , H01L29/0665 , H01L29/0673 , H01L29/78696
摘要： A semiconductor structure is provided. The semiconductor structure includes a plurality of nanostructures, a gate stack surrounding the nanostructures, a first source/drain feature and a second source/drain feature adjoining a first side and a second side of the plurality of nanostructures, respectively, a first contact plug under and electrically connected to the first source/drain feature, a second contact plug over and electrically connected to the second source/drain feature, and an insulating layer surrounding the second contact plug and covering a top surface of the first source/drain feature.
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公开(公告)号：US20240363702A1
公开(公告)日：2024-10-31
申请号：US18769646
申请日：2024-07-11
发明人： Yu-Xuan Huang , Wang-Chun Huang , Yi-Bo Liao , Cheng-Ting Chung , Hou-Yu Chen , Kuan-Lun Cheng , Wei Ju Lee
IPC分类号： H01L29/417 , H01L29/08 , H01L29/40 , H01L29/423 , H01L29/45 , H01L29/66 , H01L29/786
CPC分类号： H01L29/41733 , H01L29/0847 , H01L29/401 , H01L29/66742 , H01L29/42392 , H01L29/45 , H01L29/66545 , H01L29/78618 , H01L29/78696
摘要： In an exemplary aspect, the present disclosure is directed to a device. The device includes a semiconductor substrate, a stack of semiconductor layers over the semiconductor substrate, a gate structure over and between the stack of semiconductor layers, where the gate structure engages with the stack of semiconductor layers. Moreover, the device also includes a silicide layer extending along sidewall surfaces of the stack of semiconductor layers, and a source/drain feature on a sidewall surface of the silicide layer.
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公开(公告)号：US20240363697A1
公开(公告)日：2024-10-31
申请号：US18351784
申请日：2023-07-13
发明人： Yi-An Lai , Chan-Hong Chern , Pen Chieh Yu , Cheng-Hsiang Hsieh
IPC分类号： H01L29/40 , H01L21/311 , H01L21/3213 , H01L29/06 , H01L29/205 , H01L29/417 , H01L29/423
CPC分类号： H01L29/405 , H01L21/31105 , H01L21/3213 , H01L29/0649 , H01L29/205 , H01L29/401 , H01L29/41775 , H01L29/42316 , H01L29/66431 , H01L29/7786
摘要： Various embodiments of the present disclosure are directed towards a semiconductor device comprising a plurality of quasi field plates (QFPs) for enhanced wafer uniformity and performance. A channel layer and a barrier layer are stacked on a substrate, and the channel layer accommodates a two-dimensional carrier gas (2DCG). A source electrode, a drain electrode, and a gate electrode overlie the channel and barrier layers, and the gate electrode is between the source and drain electrodes in a first direction. The plurality of QFPs are between the gate electrode and the drain electrode. Further, the plurality of QFPs are capacitively or directly electrically coupled to the drain electrode, and are spaced from each other laterally in a line in a second direction transverse to the first direction.
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