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公开(公告)号：US20240364349A1
公开(公告)日：2024-10-31
申请号：US18767216
申请日：2024-07-09
CPC分类号： H03L7/0814 , H03L7/0818 , H03L7/095
摘要： Digital delay lock circuits and methods for operating digital delay lock circuits are provided. A phase detector is configured to receive first and second clock signals and generate a digital signal indicating a relationship between a phase of the first clock signal and a phase of the second clock signal. A phase accumulator circuit is configured to receive the digital signal and generate a phase signal based on values of the digital signal over multiple clock cycles. A decoder is configured to receive the phase signal and generate a digital control word based on the phase signal. A delay element is configured to receive the digital control word. The delay element is further configured to change the relationship between the phase of the first clock signal and the phase of the second clock signal by modifying the phase of the second clock signal according to the digital control word.
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公开(公告)号：US20240361371A1
公开(公告)日：2024-10-31
申请号：US18767283
申请日：2024-07-09
CPC分类号： G01R29/023 , G01R25/005 , H03K3/037 , H03K5/00 , H03K19/21 , H03K2005/00058
摘要： Systems, methods, and circuits for determining a duty cycle of a periodic input signal are provided. A delay element is configured to delay the periodic input signal based on a digital control word. A digital circuit is configured to generate a first digital control word used to delay the periodic input signal a first amount of time corresponding to a period of the periodic input signal, generate a second digital control word used to delay the periodic input signal a second amount of time corresponding to a portion of the periodic input signal having a logic-level high value, and generate a third digital control word used to delay the periodic input signal a third amount of time corresponding to a portion of the periodic input signal having a logic-level low value. A controller is configured to determine the duty cycle based on the first, second, and third digital control words.
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公开(公告)号：US12068306B2
公开(公告)日：2024-08-20
申请号：US18312219
申请日：2023-05-04
IPC分类号： H01L27/02 , G06F30/3953 , H01L23/522 , H01L23/528
CPC分类号： H01L27/0207 , G06F30/3953 , H01L23/5226 , H01L23/528
摘要： An integrated circuit (IC) device includes a substrate having opposite first and second sides, an active region over the first side of the substrate, a first transistor and a second transistor over the first side of the substrate, a first conductive pattern over the first side of the substrate, and a second conductive pattern under the second side of the substrate. The first conductive pattern electrically couples a first terminal of the first transistor to a second terminal of the second transistor. The second conductive pattern electrically couples the first terminal of the first transistor to the second terminal of the second transistor.
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公开(公告)号：US11962441B2
公开(公告)日：2024-04-16
申请号：US17814641
申请日：2022-07-25
发明人： Chaitanya Palusa , Rob Abbott , Wei-Li Chen , Po-Hsiang Lan , Dirk Pfaff , Cheng-Hsiang Hsieh
CPC分类号： H04L25/03878 , H03K5/135 , H04L25/028 , H04L25/03038 , H04L25/03057 , H04L27/01 , H03K2005/00052 , H03K2005/00065
摘要： A multi-tap Differential Feedforward Equalizer (DFFE) configuration with both precursor and postcursor taps is provided. The DFFE has reduced noise and/or crosstalk characteristics when compared to a Feedforward Equalizer (FFE) since DFFE uses decision outputs of slicers as inputs to a finite impulse response (FIR) unlike FFE which uses actual analog signal inputs. The digital outputs of the tentative decision slicers are multiplied with tap coefficients to reduce noise. Further, since digital outputs are used as the multiplier inputs, the multipliers effectively work as adders which are less complex to implement. The decisions at the outputs of the tentative decision slicers are tentative and are used in a FIR filter to equalize the signal; the equalized signal may be provided as input to the next stage slicers. The bit-error-rate (BER) of the final stage decisions are lower or better than the BER of the previous stage tentative decisions.
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公开(公告)号：US11676957B2
公开(公告)日：2023-06-13
申请号：US17189908
申请日：2021-03-02
IPC分类号： H01L27/02 , G06F30/3953 , H01L23/528 , H01L23/522
CPC分类号： H01L27/0207 , G06F30/3953 , H01L23/528 , H01L23/5226
摘要： An integrated circuit (IC) device includes a substrate having opposite first and second sides, an active region over the first side of the substrate, a first conductive pattern over the active region, and a second conductive pattern under the second side of the substrate. The active region includes a first portion and a second portion. The first conductive pattern is electrically coupled to the first portion and the second portion of the active region. The second conductive pattern is electrically coupled to the first portion and the second portion of the active region.
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公开(公告)号：US11240075B2
公开(公告)日：2022-02-01
申请号：US17157114
申请日：2021-01-25
发明人： Chaitanya Palusa , Rob Abbott , Rolando Ramirez , Wei-Li Chen , Dirk Pfaff , Cheng-Hsiang Hsieh , Fan-ming Kuo
摘要： An optimized pulse shaping clock data recovery system is provided that includes a slicer configured to receive a signal and provide an initial set of tentative decisions to a decision feedforward equalizer, where the decision feedforward equalizer provides a fully equalized output signal. The slicer may be incorporated as part of decision feedback equalizer to provide better quality tentative decisions. The clock data recovery system also receives the first output signal that is partially equalized in such a way as to optimally shape it for a clock to sample it at an ideal location by providing an adjustment signal to the analog to digital controller.
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公开(公告)号：US11228303B2
公开(公告)日：2022-01-18
申请号：US17065593
申请日：2020-10-08
IPC分类号： H03K3/03
摘要： A controlling circuit for ring oscillator is provided. First and second transistors of a first conductive type are coupled in series and between a node and a first power source. Third and fourth transistors of a second conductive type are coupled in parallel and between the node and a second power source. The node is coupled to an input of a delay chain of the ring oscillator. The second and third transistors are coupled in series and gates of the second and third transistors are configured to receive an output signal of the delay chain. When the first transistor is turned off and the fourth transistor is turned on, the node is pulled to a first logic level from a second logic level in order to align a phase of a waveform of the ring oscillator.
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公开(公告)号：US20200252248A1
公开(公告)日：2020-08-06
申请号：US16741188
申请日：2020-01-13
发明人： Chaitanya Palusa , Rob Abbott , Rolando Ramirez , Wei-Li Chen , Dirk Pfaff , Cheng-Hsiang Hsieh , Fan-ming Kuo
摘要： An optimized pulse shaping clock data recovery system is provided that includes a slicer configured to receive a signal and provide an initial set of tentative decisions to a decision feedforward equalizer, where the decision feedforward equalizer provides a fully equalized output signal. The slicer may be incorporated as part of decision feedback equalizer to provide better quality tentative decisions. The clock data recovery system also receives the first output signal that is partially equalized in such a way as to optimally shape it for a clock to sample it at an ideal location by providing an adjustment signal to the analog to digital controller.
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公开(公告)号：US12057846B2
公开(公告)日：2024-08-06
申请号：US18301299
申请日：2023-04-17
CPC分类号： H03L7/0814 , H03L7/0818 , H03L7/095
摘要： Digital delay lock circuits and methods for operating digital delay lock circuits are provided. A phase detector is configured to receive first and second clock signals and generate a digital signal indicating a relationship between a phase of the first clock signal and a phase of the second clock signal. A phase accumulator circuit is configured to receive the digital signal and generate a phase signal based on values of the digital signal over multiple clock cycles. A decoder is configured to receive the phase signal and generate a digital control word based on the phase signal. A delay element is configured to receive the digital control word. The delay element is further configured to change the relationship between the phase of the first clock signal and the phase of the second clock signal by modifying the phase of the second clock signal according to the digital control word.
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公开(公告)号：US20230403001A1
公开(公告)日：2023-12-14
申请号：US17835688
申请日：2022-06-08
发明人： Yi-An Lai , Chan-Hong Chern , Cheng-Hsiang Hsieh
IPC分类号： H03K17/0812 , H02H9/04
CPC分类号： H03K17/08128 , H03K17/08122 , H02H9/04
摘要： A switching circuit includes a main circuit including a number of first transistors. The main circuit has a first node, a second node, and a third node and is operative in response to a control signal received by the first node, and the second node is configured to receive a supply voltage. The switching circuit also includes an auxiliary circuit electrically coupled to the second node of the main circuit and configured to provide surge protection for the main circuit. The auxiliary circuit includes a second transistor. A breakdown voltage of the second transistor is different than a breakdown voltage of each first transistor of the number of first transistors.
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