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公开(公告)号：US20240356536A1
公开(公告)日：2024-10-24
申请号：US18206093
申请日：2023-06-06
摘要： A device for correcting a duty cycle, comprising: a duty adjustor circuit, configured to receive an input clock signal and a tuning signal, to generate an output clock signal; a first charge pump, configured to charge a first capacitor for a predetermined time period to generate a first voltage; a second charge pump, configured to charge a second capacitor for a time period corresponding to the duty cycle of the output clock signal to generate a second voltage; a first sampling and hold circuit, configured to sample the first voltage to generate a first sampled voltage; a second sampling and hold circuit, configured to sample the second voltage to generate a second sampled voltage; and an error amplifier, configured to generate the tuning signal according to a difference value between the first sampled voltage and the second sampled voltage.
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公开(公告)号：US20240313941A1
公开(公告)日：2024-09-19
申请号：US18585216
申请日：2024-02-23
发明人： Makoto UMEHARA
摘要： A communication apparatus according to an embodiment of the present disclosure includes: a ring-shaped transmission path which is disposed in one of a fixed part and a rotating part and includes a plurality of transmission paths each configured to transmit transmission data including a transmission signal and a clock signal; a first coupler disposed in the other of the fixed part and the rotating part and configured to receive the transmission data from one of the plurality of transmission paths; a determining unit configured to determine a regenerated clock signal based on the clock signal in accordance with a reception position in which the first coupler receives the transmission data from the one of the transmission paths; and a data generating unit configured to generate reception data on the basis of the transmission signal received by the first coupler and the regenerated clock signal.
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公开(公告)号：US12068750B2
公开(公告)日：2024-08-20
申请号：US18180582
申请日：2023-03-08
发明人： Satoshi Takaya , Hiroaki Ishihara
CPC分类号： H03K5/135 , H03K5/00006 , H03K2005/00286
摘要： According to one embodiment, an electronic circuitry includes a clock generation circuit configured to generate a first clock signal; a first conversion circuit configured to convert an input signal into a first signal having a frequency corresponding to the first clock signal based on the first clock signal; a first electromagnetic field coupler configured to transmit the first signal by electromagnetic field coupling; a second electromagnetic field coupler configured to transmit the first clock signal by electromagnetic field coupling; and a second conversion circuit configured to convert the first signal transmitted by the first electromagnetic field coupler into a second signal having a frequency corresponding to the input signal, based on the first clock signal transmitted by the second electromagnetic field coupler.
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公开(公告)号：US12057841B1
公开(公告)日：2024-08-06
申请号：US18173822
申请日：2023-02-24
发明人： Bal S. Sandhu
CPC分类号： H03K3/0377 , H03K5/1252 , H03K5/133 , H03K5/135 , H03K21/00
摘要： A circuit receives an input clock pulse signal characterized by a first frequency and a first pulse width, and produces an output pulse signal characterized by a second frequency that is half of the first frequency and a second pulse width that is equal to the first pulse width. The circuit also includes a first D-flipflop, a first inverter, a first Schmitt trigger, and a first AND gate. The first D-flipflop includes a clock input terminal for receiving the input clock pulse signal and an output terminal for producing a first data output. The first inverter couples the output terminal and a data input terminal of the first D-flipflop. A first Schmitt trigger receives the input clock pulse signal and provides a first delayed input clock signal. The first AND gate receives the first data output and the first delayed input clock signal, and provides the output pulse signal.
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公开(公告)号：US12028076B1
公开(公告)日：2024-07-02
申请号：US18174823
申请日：2023-02-27
发明人： Richard Ernest Geiss
CPC分类号： H03K5/135 , H03K2005/00019
摘要： A circuit and corresponding method for determining a delay are presented. The circuit includes a delay circuit, a feedback circuit and a controller. The delay circuit receives an input signal having an input edge and provides an output signal having an output edge. The input edge and the output edge are separated by a delay. The feedback circuit causes the delay circuit to generate a series of consecutive output pulses. The controller sets the delay to a first delay value and measures a first period of output pulses; sets the delay to a second delay value and measure a second period of output pulses. The controller then calculates the delay based on a difference between the first period and the second period.
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公开(公告)号：US11996844B2
公开(公告)日：2024-05-28
申请号：US18106915
申请日：2023-02-07
申请人： SK hynix Inc.
发明人： Dae Ho Yang , Min Su Kim , Kwan Su Shon , Keun Seon Ahn , Soon Sung An , Su Han Lee , Jae Hoon Jung , Kyeong Min Chae , Jae Hyeong Hong , Jun Sun Hwang
CPC分类号： H03K3/017 , H03K5/05 , H03K5/135 , H03K5/1565
摘要： A duty cycle correction circuit includes a duty correction circuit, an information generation circuit and a duty control circuit. The duty correction circuit corrects a duty rate of an input clock signal based on a duty control code to generate an output clock signal. The information generation circuit compares a difference between operation power voltages based on an operation mode to generate voltage information. The duty control circuit receives the voltage information from the information generation circuit and generates the duty control code that includes the voltage information based on a duty rate of the output clock signal.
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公开(公告)号：US20240171167A1
公开(公告)日：2024-05-23
申请号：US18496495
申请日：2023-10-27
申请人： Media Tek Inc.
发明人： Ahmed Safwat Mohamed Aboelenein Elmallah , Amr Tarek Ahmed Abdelrazik Khashaba , Mohammed Mohsen Abdulsalam Abdullatif , Tamer Mohammed Ali
摘要： A digitally controlled delay device includes a plurality of first delay stages connected in series between a first input port and a first output port, and a plurality of second delay stages connected in series between a second input port and a second output port. Each first delay stage of the plurality of first delay stages includes a plurality of first delay elements and each second delay stage of the plurality of second delay stages includes a corresponding plurality of second delay elements. A controller performs complementary control based on a digital control signal by controlling one or more of the plurality of first delay elements to be in a first control state and controlling a corresponding one or more of the plurality of second delay elements to be in a second control state, opposite the first control state.
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公开(公告)号：US20240143060A1
公开(公告)日：2024-05-02
申请号：US18408548
申请日：2024-01-09
申请人： MAXLINEAR, INC.
发明人： Chunfeng Hu , Rajan Raghvendra
CPC分类号： G06F1/324 , G06F1/08 , H03K5/135 , G06F1/3203
摘要： Systems, methods, and circuitries are disclosed generating a dynamic clock signal having a dynamic clock signal frequency for a data processing system from an input clock signal having an input clock signal frequency. In one example, adaptive frequency scaling circuitry includes scaling control circuitry and clock gating circuitry. The scaling control circuitry includes hardware configured to receive a performance indicator value indicative of an operating parameter of the data processing system and select a dynamic clock gating control value based at least on the performance indicator value. The clock gating circuitry is configured to receive the dynamic clock gating control value, and in response, selectively gate the input clock signal based on the dynamic clock gating control value to generate the dynamic clock signal.
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9.发明授权公开(公告)号：US11973504B2
公开(公告)日：2024-04-30
申请号：US17762677
申请日：2020-08-17
申请人： Intel Corporation
发明人： Leon Zlotnik , Lev Zlotnik , Jeremy Anderson
IPC分类号： H03K5/135 , G06F1/24 , H03K19/17704 , H03K19/20
CPC分类号： H03K5/135 , G06F1/24 , H03K19/17716 , H03K19/20
摘要： An asynchronous multi-cycle reset synchronization circuit that can correlate any number of resets and synchronous clocks with simultaneous reset de-assertion and removal of reset assertion crossing hazards. The asynchronous multi-cycle reset synchronization circuit can also be paired with a synchronous multi-cycle reset synchronization circuit to correlate same domain asynchronous and synchronous resets. Also described is a synchronous reset multi-cycle synchronization circuit that correlates with any number of asynchronous resets and guarantees simultaneous reset de-assertion.
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公开(公告)号：US20240125895A1
公开(公告)日：2024-04-18
申请号：US18531325
申请日：2023-12-06
申请人： Novelda AS
摘要： A pulse generator comprising: a first signal generating arm comprising a first inductor and a plurality of switching elements, each arranged to draw current through the first inductor; and a controller arranged to activate the plurality of switching elements in a predetermined sequence so as to generate a predetermined pulse waveform at a pulse generator output. The switching elements of the signal generating arm and the inductor together form a pulse synthesizer that takes the signal from the controller and uses it to synthesize an output pulse. Compared with conventional transmitter architectures, the functions of the upconversion mixer, the DAC, and the power amplifier are all performed by a single simplified circuit. This is both area efficient and power efficient.
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