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    PIPELINE CLOCK DRIVING CIRCUIT, COMPUTING CHIP, HASHBOARD AND COMPUTING DEVICE
    1.
    发明公开
    PIPELINE CLOCK DRIVING CIRCUIT, COMPUTING CHIP, HASHBOARD AND COMPUTING DEVICE 审中-公开

    公开(公告)号：US20240313753A1

    公开(公告)日：2024-09-19

    申请号：US17795777

    申请日：2021-12-21

    申请人： SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD.

    发明人： Nan LI ,  Zhijun FAN ,  Chao XU ,  Lianhua DUAN ,  Haifeng GUO

    IPC分类号： H03K5/14 ,  H03K5/24 ,  H03K19/20

    CPC分类号： H03K5/14 ,  H03K5/2481 ,  H03K19/20

    摘要： This disclosure relates to a pipeline clock driving circuit, a computing chip, a hashboard and a computing device. A pipeline clock driving circuit provides a pulse clock signal to a pipeline comprising multiple operation stages. The pipeline clock driving circuit includes multiple stages of clock driving circuits, each configured to provide the pulse clock signal to one corresponding operation stage; and a clock source coupled to an input of a first stage of clock driving circuit and configured to provide a basic clock signal. Inputs of other stages of clock driving circuits are coupled to outputs of previous stages of clock driving circuits. Each stage of clock driving circuit includes: a trigger; a delay module for outputting a delayed pulse signal to a next stage of clock driving circuit; and a combinational logic module for performing a combinational logic operation on the outputs to generate the pulse clock signal.

    GAIN CALIBRATION OF DIGITALLY CONTROLLED DELAY LINE
    3.
    发明公开
    GAIN CALIBRATION OF DIGITALLY CONTROLLED DELAY LINE 审中-公开

    公开(公告)号：US20240171166A1

    公开(公告)日：2024-05-23

    申请号：US18493378

    申请日：2023-10-24

    申请人： Media Tek Inc.

    发明人： Ahmed Safwat Mohamed Aboelenein Elmallah ,  Amr Tarek Ahmed Abdelrazik Khashaba ,  Mohammed Mohsen Abdulsalam Abdullatif ,  Tamer Mohammed Ali

    IPC分类号： H03K5/14 ,  H03L7/099

    CPC分类号： H03K5/14 ,  H03L7/099 ,  H03K2005/00058

    摘要： A system to operate as a phase locked loop (PLL) includes a frequency synthesizer in a feedback path of the PLL and a delay line arranged to receive an output of the frequency synthesizer. A retimer subsystem is arranged to receive the output of the frequency synthesizer. A digitally controlled delay line (DCDL) is arranged to receive an output of the retimer. A phase detector is arranged to receive an output of the delay line and an output of the DCDL and to provide an error signal indicating a difference in phase of the output of the delay line relative to the output of the DCDL. A controller causes closed loop operation of the PLL during a normal operational mode and open loop operation during a calibration mode during which gain of the DCDL, defining a relationship between a control code and a resulting delay, is calibrated.

    Digital droop detector
    4.
    发明授权
    Digital droop detector 有权

    公开(公告)号：US11927612B1

    公开(公告)日：2024-03-12

    申请号：US18048018

    申请日：2022-10-19

    申请人： Marvell Asia Pte Ltd

    发明人： Ernest Knoll ,  Omer Yassur

    IPC分类号： G01R25/00 ,  H03K5/14 ,  H03L7/00

    CPC分类号： G01R25/005 ,  H03K5/14 ,  H03L7/00

    摘要： A circuit detects a voltage droop exhibited by a power supply. A first signal delay line outputs a first delayed signal, and is comprised of delay elements having a first threshold voltage. A second delay line outputs a second delayed signal, and is comprised of delay elements having a second threshold voltage that is higher than the first threshold voltage. A phase detector compares the first and second delayed signals and outputs a comparison signal indicating which of the first and second signal delay lines exhibits a shorter delay. A reset circuit resets the first and second signal delay lines in response to the comparison signal, and a clock controller outputs a command to adjust a clock frequency or engage in other mitigation measures based on the comparison signal.

    LOW-POWER INTER-DIE COMMUNICATION USING DELAY LINES
    5.
    发明公开
    LOW-POWER INTER-DIE COMMUNICATION USING DELAY LINES 审中-公开

    公开(公告)号：US20240056067A1

    公开(公告)日：2024-02-15

    申请号：US18323942

    申请日：2023-05-25

    申请人： QUALCOMM Incorporated

    发明人： Sameer WADHWA ,  Lennart Karl-Axel MATHE

    IPC分类号： H03K5/14 ,  H03K5/1534 ,  H03K5/19

    CPC分类号： H03K5/14 ,  H03K5/1534 ,  H03K5/19 ,  H03K5/15033

    摘要： A low-power phase interpolator circuit has a phase generator that receives an input clock signal and uses the input clock signal to generate multiple intermediate clock signals with different phase shifts; a phase rotator circuit that outputs phase-adjusted clock signals, each phase-adjusted clock signal having a phase that lies within a range bounded by phases of two of the intermediate clock signals; a frequency doubler circuit that receives a plurality of the phase-adjusted clock signals and outputs two frequency-doubled clock signals having a 180° phase difference; and a quadrature clock generation circuit that receives the two frequency-doubled clock signals and provides four output signals that include in-phase and quadrature versions of the two frequency-doubled clock signals.

    DELAY CIRCUIT AND SEMICONDUCTOR MEMORY
    6.
    发明公开
    DELAY CIRCUIT AND SEMICONDUCTOR MEMORY 审中-公开

    公开(公告)号：US20230378948A1

    公开(公告)日：2023-11-23

    申请号：US18230096

    申请日：2023-08-03

    申请人： Changxin Memory Technologies, Inc.

    发明人： Yu YANG

    IPC分类号： H03K5/14 ,  G11C7/22 ,  H03K19/21 ,  G11C7/04

    CPC分类号： H03K5/14 ,  G11C7/222 ,  H03K19/21 ,  G11C7/04 ,  H03K2005/00058

    摘要： Delay circuitry includes a temperature compensation control circuit and a delay circuit. The temperature compensation control circuit is configured to generate a target temperature compensation control signal based on an initial control signal, a real-time ambient temperature signal, a temperature coefficient compensation enable signal, and a temperature coefficient control signal. The delay circuit is connected to the temperature compensation control circuit, and is configured to generate a temperature compensated target delay signal based on the target temperature compensation control signal and an initial delay signal such that a delay time of the target delay signal generated by the delay circuit can be dynamically compensated based on a real-time ambient temperature signal collected by a temperature sensor.

    Clock detecting circuit
    8.
    发明授权
    Clock detecting circuit 有权

    公开(公告)号：US11736099B1

    公开(公告)日：2023-08-22

    申请号：US17887495

    申请日：2022-08-14

    申请人： NANYA TECHNOLOGY CORPORATION

    发明人： Chang-Ting Wu

    IPC分类号： H03K5/00 ,  H03K5/24 ,  H03K19/17784 ,  H03K5/1534 ,  H03K5/14 ,  H03K5/26

    CPC分类号： H03K5/2472 ,  H03K5/14 ,  H03K5/1534 ,  H03K5/26 ,  H03K19/17784

    摘要： A clock detecting circuit is provided. The clock detecting circuit includes a first clock converting circuit, a second clock converting circuit and a frequency comparator. The first clock converting circuit converts an internal clock to a first clock. The second clock converting circuit converts an external clock to a second clock. The frequency comparator generates a first edge clock in response the first clock and generates a second edge clock in response the second clock. The frequency comparator generates a first sensing voltage in response to a plurality of positive pulses of the first edge clock and generate a second sensing voltage in response to a plurality of positive pulses of the second edge clock. The frequency comparator compares the first sensing voltage and the second sensing voltage to provide a frequency comparing result between the external clock and the internal clock.

    CLOCK SYNTHESIS, DISTRIBUTION, AND MODULATION TECHNIQUES
    10.
    发明申请
    CLOCK SYNTHESIS, DISTRIBUTION, AND MODULATION TECHNIQUES 有权

    公开(公告)号：US20230093490A1

    公开(公告)日：2023-03-23

    申请号：US17800876

    申请日：2021-02-23

    申请人： The University of British Columbia

    发明人： Ahmad Sharkia ,  Sudip Shekhar ,  Shahriar Mirabbasi

    IPC分类号： H03K5/14 ,  H03K4/08 ,  H03K21/08

    摘要： A “frequency shifter” is a clock synthesis system, that includes either a multiplexer or a multi-modulus divider (MMD), a fractional frequency divider, a tunable delay element, a sawtooth signal generator, in addition to other synchronization and control circuits. The generated sawtooth signal is used to control the delay of the tunable delay element, which in turn is used to adjust the phase of the signal generated by either M-to-1 multiplexer or the MMD, reducing its timing errors, and improving the spectral purity of the generated clock signal.