公开(公告)号：US12237829B2

公开(公告)日：2025-02-25

申请号：US18086534

申请日：2022-12-21

Applicant: XILINX, INC.

Inventor： Abhirup Lahiri ,  Christophe Erdmann

IPC: H03M1/12 ,  H03K17/687 ,  H03K5/00 ,  H03K5/01

Abstract: An electronic system includes a source follower circuitry that functions as an input driver. The source follower circuitry includes a first input transistor, first current source circuitry, and first phase shift circuitry. The first input transistor includes a first node coupled to a first voltage node, a second node coupled to a first output node, and a gate node coupled to a first input node. The gate node receives a first input signal via the first input node. The first current source circuitry coupled to the first output node and configured to generate a first bias current. The first phase shift circuitry is coupled to the first current source circuitry. The first phase shift circuitry generates a first phase shift signal to modulate the first current source circuitry to reduce signal drop across the first input transistor.

公开(公告)号：US20250062940A1

公开(公告)日：2025-02-20

申请号：US18395631

申请日：2023-12-25

Applicant: PowerX Semiconductor Corporation

Inventor： Yong Cyuan CHEN ,  Jui Teng CHAN ,  Chung-Kang WU

IPC: H03K7/06 ,  H03K5/00 ,  H03K7/08

Abstract: The present disclosure provides an isolation integrated circuit, a carrier frequency control circuit and a modulation signal generation method. The isolation integrated circuit includes a carrier frequency generation circuit, a carrier frequency control circuit and a modulation circuit. The carrier frequency generation circuit generates a carrier frequency signal. The carrier frequency control circuit detects enabling periods and disabling periods of an input signal, controls the carrier frequency generation circuit to output the carrier frequency signal during the enabling periods, and controls the carrier frequency generation circuit to stop outputting the carrier frequency signal in the output periods of timing pulses during the disabling periods. The timing pulses are generated in response to detection of entering the disabling periods. The modulation circuit receives the input signal and the carrier frequency signal, and outputs a modulation signal according to the input signal and the carrier frequency signal.

公开(公告)号：US12218672B2

公开(公告)日：2025-02-04

申请号：US18092091

申请日：2022-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Michael Henderson Perrott

IPC: H03K5/14 ,  H03K5/00 ,  H03L7/08

Abstract: In some examples, an apparatus includes a delay-based frequency multiplier and an error detection circuit. The delay-based frequency multiplier has a clock input, a multiplier clock output, and a delay calibration input. The error detection circuit has a detection input and a detection output. The detection input is coupled to the multiplier clock output, and the detection output is coupled to the delay calibration input. The error detection circuit is configured to receive a clock signal at the detection input, and provide a period error signal at the detection output based on a time difference between a first edge of the clock signal and a second edge of a delayed version of the clock signal.

公开(公告)号：US20250030410A1

公开(公告)日：2025-01-23

申请号：US18429773

申请日：2024-02-01

Applicant: NXP USA, Inc.

Inventor： Neha Srivastava ,  Kumar Abhishek ,  Nishant Kumar

IPC: H03K5/133 ,  H03K5/00 ,  H03K5/135

Abstract: A first circuit path communicates a first, asynchronous, signal, and a second path communicates a second signal. A schmoo delay circuit receives the first and second signals and includes shmoo control circuitry and a delay generator. The delay generator receives a delay selector signal from the shmoo control circuitry indicative of an amount of delay. The shmoo delay circuit provides a delayed version of at least one of the first or second signals. A first logic circuit receives the delayed version of the at least one of the first signal or the second signal, and a second logic circuit receives another one of the first signal or the second signal. The shmoo control circuitry modifies the delay selector signal to sweep through a set of different delay amounts applied by the delay generator to generate delayed versions of the at least one of the first signal or the second signal.

公开(公告)号：US12191861B2

公开(公告)日：2025-01-07

申请号：US18169138

申请日：2023-02-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nilanjan Pal ,  Saurav Bandyopadhyay

IPC: H03K5/01 ,  H03K5/24 ,  H03K17/56 ,  H03K5/00

Abstract: A circuit includes a comparator having first and second comparator inputs and a comparator output. A discharge switch is coupled between the first comparator input and a ground terminal. A capacitor has first and second capacitor terminals, in which the first capacitor terminal is coupled to the first comparator input. A delay correction circuit includes a sample-hold circuit coupled to the first capacitor terminal and the second capacitor terminal. An amplifier has a first amplifier input coupled to a hold output of the sample-hold circuit and a second amplifier input coupled to the second comparator input. A variable resistor is coupled between the second capacitor terminal and the ground terminal, and has a control input coupled to the amplifier output.

公开(公告)号：US12188982B2

公开(公告)日：2025-01-07

申请号：US17860216

申请日：2022-07-08

Applicant: REALTEK SEMICONDUCTOR CORP.

Inventor： Kuo-Wei Chi ,  Chun-Chi Yu ,  Chih-Wei Chang

IPC: G01R31/317 ,  H03K3/037 ,  H03K5/00 ,  H03K21/08

Abstract: A test method for a delay circuit and a test circuitry are provided. The test circuitry incudes the delay circuit that essentially includes multiple serially connected logic gates, a clock pulse generator at an input end of the delay circuit for generating one or more cycles of clock signals, and a counter at an output end of the delay circuit for counting the clock signals passing through the delay circuit. The test circuitry implements a test mode by switching lines to the clock pulse generator and the counter. The test circuitry relies on a comparison result of a counting result made by the counter and a number of the cycles of the clock signals to test any failure of the delay circuit.

公开(公告)号：US12164326B2

公开(公告)日：2024-12-10

申请号：US18168622

申请日：2023-02-14

Applicant: NXP B.V.

Inventor： Vishwajit Babasaheb Bugade ,  Anand Kumar Sinha ,  Krishna Thakur ,  Siyaram Sahu

IPC: H03K5/01 ,  G06F1/08 ,  H03K5/00

Abstract: A phase shifted clock generator that includes a delay circuit, a capacitor, and a control circuit is provided. The delay circuit receives a reference clock signal and generates a phase shifted clock signal. A phase difference between the phase shifted clock signal and the reference clock signal is controlled based on a delay of the delay circuit. The control circuit controls, based on the phase shifted clock signal and the reference clock signal, a control voltage generated at the capacitor. The control circuit controls the control voltage by charging and discharging the capacitor with a constant current. The delay of the delay circuit is controlled based on the control voltage such that the phase difference between the phase shifted clock signal and the reference clock signal is within a predefined range.

公开(公告)号：US12160231B2

公开(公告)日：2024-12-03

申请号：US18310805

申请日：2023-05-02

Applicant: Lodestar Licensing Group LLC

Inventor： Raghukiran Sreeramaneni ,  Daniel B. Penney

IPC: H03K5/00 ,  G11C11/4093 ,  H03K5/01 ,  H03K5/1252 ,  H03K17/687

Abstract: An input receiver circuit for a signal line may receive inputs from other signal lines to mitigate crosstalk noise present on the signal line. In some examples, the input receiver circuit may include a transistor with a programmable width. In some examples, the input receiver circuit may include a bias current generator with a programmable current. The width and/or current may be programmed based on an amount of crosstalk noise introduced by the other signal line. In some examples, the input receiver circuit may include a resistance and/or a capacitance. In some examples the resistor and/or capacitor may be programmable. The resistance and/or capacitance may be programmed based on a duration of the crosstalk noise on the signal line.

公开(公告)号：US20240361800A1

公开(公告)日：2024-10-31

申请号：US18631738

申请日：2024-04-10

Applicant: STMicroelectronics S.r.l.

Inventor： Juri Giovannone ,  Roberto Giorgio Bardelli ,  Andrea Gambero ,  Alessio Corso ,  Donata Rosaria Maria Nicolosi

IPC: G06F1/10 ,  G04F10/00 ,  G06F1/12 ,  H03K5/00

CPC classification number: G06F1/10 ,  G04F10/005 ,  G06F1/12 ,  H03K5/00 ,  H03K2005/00013

Abstract: The present invention relates to a system and a method for generating a plurality of control signals for multi-die applications. In particular, the invention relates to the generation of synchronized control signals generated by independent dies having an own local clock and provided with a common clock. In a first step, in each die, the period of the common clock signal is measured using a TDC. In further steps, in each die, a respective phase shift is evaluated and applied between the rising edge of the common clock signal and each of the rising edges of the output control signals, using delay unit.

公开(公告)号：US12119825B2

公开(公告)日：2024-10-15

申请号：US17780618

申请日：2019-12-10

Applicant: Telefonaktiebolaget LM Ericsson (publ)

Inventor： Mingquan Bao ,  Yinggang Li

IPC: H03K5/00 ,  H03H11/04 ,  H03K17/60 ,  H03K17/687

CPC classification number: H03K5/00006 ,  H03H11/0405 ,  H03K17/60 ,  H03K17/6871

Abstract: Frequency multipliers (300) for generating a differential output signal from a single-ended input signal are disclosed. The frequency multiplier comprises a single-ended input (Pin(f0)) to receive the input signal with a frequency of f0 and differential outputs (+/−Pout(2nf0)) to provide the differential output signals. The frequency multiplier further comprises a first signal branch (301) connected to the single-ended input and one of the differential outputs (+Pout(2nf0)). The first signal branch comprises a first low pass or bandpass filter with a center frequency of f0 (L/BPF1), a first nonlinear component (NC1) and a first high pass or bandpass filter with a center frequency of 2nf0 (H/BPF1). The frequency multiplier further comprises a second signal branch connected to the single-end input and another one of the differential outputs (−Pout(2nf0)). The second signal branch comprises a second low pass or bandpass filter with a center frequency of f0 (L/BPF1), a second nonlinear component (NC2) and a second high pass or bandpass filter with a center frequency of 2nf0 (H/BPF2). The first and second nonlinear components are configured such that even-order harmonics generated in the first and second nonlinear components are in anti-phase, thereby the differential output signals with a frequency of 2n times the frequency of the input signal are generated at the differential output, where n is an integer number.