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公开(公告)号:US20220224348A1
公开(公告)日:2022-07-14
申请号:US17461997
申请日:2021-08-31
Applicant: Texas Instruments Incorporated
Inventor: Michael Henderson Perrott , Hon Kin Chiu
IPC: H03M1/08 , H03M1/06 , H03M1/18 , G11C11/4099 , G11C11/4093
Abstract: In described examples, a feedback loop has phase detection (PD) circuitry that has a reference input to receive a reference frequency signal, a feedback input to receive a feedback signal, and phase difference outputs. A phase to digital converter (P2DC) includes a first phase to charge converter (PCC) that has a gain polarity and a first phase error output; a second PCC that has an opposite gain polarity and a second phase error output. A differential loop filter has an amplifier with an inverting input coupled to the first phase error output and a non-inverting input coupled to the second phase error output. An analog to digital converter (ADC) has an input coupled to an output of the differential loop filter. A feedback path is coupled to the output of the P2DC, with an output of the feedback path providing the feedback signal to the PD feedback input.
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公开(公告)号:US11601089B1
公开(公告)日:2023-03-07
申请号:US17463406
申请日:2021-08-31
Applicant: Texas Instruments Incorporated
Inventor: Michael Henderson Perrott , Ting-Ta Yen , Bichoy Bahr , Baher S. Haroun
Abstract: A temperature compensated oscillator circuit includes a first oscillator, a second oscillator, a first divider, a second divider, a frequency ratio circuit, and a temperature compensation circuit. The first divider is coupled to the first oscillator, and is configured to divide a frequency of a first oscillator signal generated by the first oscillator. The second divider is coupled to the second oscillator, and is configured to divide a frequency of a second oscillator signal generated by the second oscillator. The frequency ratio circuit is coupled to the first divider and the second divider, and is configured to determine a frequency ratio of an output of the first divider to an output of the second divider. The temperature compensation circuit is coupled to the frequency ratio circuit and the first oscillator, and is configured to generate a compensated frequency based on the frequency ratio and the first oscillator signal.
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公开(公告)号:US11870446B2
公开(公告)日:2024-01-09
申请号:US17461997
申请日:2021-08-31
Applicant: Texas Instruments Incorporated
Inventor: Michael Henderson Perrott , Hon Kin Chiu
IPC: H03M1/12 , H03L7/08 , H03L7/107 , H03L7/081 , H03L7/187 , H03L7/04 , G11C11/4093 , G11C11/4099 , H03M1/06 , H03M1/08 , H03M1/18
CPC classification number: H03L7/0807 , G11C11/4093 , G11C11/4099 , H03L7/04 , H03L7/0816 , H03L7/1072 , H03L7/187 , H03M1/0626 , H03M1/0687 , H03M1/0836 , H03M1/182
Abstract: In described examples, a feedback loop has phase detection (PD) circuitry that has a reference input to receive a reference frequency signal, a feedback input to receive a feedback signal, and phase difference outputs. A phase to digital converter (P2DC) includes a first phase to charge converter (PCC) that has a gain polarity and a first phase error output; a second PCC that has an opposite gain polarity and a second phase error output. A differential loop filter has an amplifier with an inverting input coupled to the first phase error output and a non-inverting input coupled to the second phase error output. An analog to digital converter (ADC) has an input coupled to an output of the differential loop filter. A feedback path is coupled to the output of the P2DC, with an output of the feedback path providing the feedback signal to the PD feedback input.
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公开(公告)号:US11784649B2
公开(公告)日:2023-10-10
申请号:US17461996
申请日:2021-08-31
Applicant: Texas Instruments Incorporated
Inventor: Michael Henderson Perrott , Robert Karl Butler
IPC: H03L7/06 , H03L7/08 , H03L7/107 , H03L7/081 , H03L7/187 , H03L7/04 , G11C11/4093 , G11C11/4099 , H03M1/06 , H03M1/08 , H03M1/18
CPC classification number: H03L7/0807 , G11C11/4093 , G11C11/4099 , H03L7/04 , H03L7/0816 , H03L7/1072 , H03L7/187 , H03M1/0626 , H03M1/0687 , H03M1/0836 , H03M1/182
Abstract: In described examples, a phase locked loop (PLL) has a first phase detector cell (PD) that has a gain polarity. The first PD cell has a phase error output and inputs coupled to a reference frequency signal and a feedback signal. A second PD cell has an opposite gain polarity. The second PD cell has a phase error output and inputs coupled to the reference frequency signal and the feedback signal. A loop filter has a feedforward path and a (lossy) integrating path coupled to an output of the filter. The feedforward path has a third PD cell that has phase error output AC-coupled to the filter output. The integrating path includes an opamp that has an inverting input coupled to the first PD cell phase error output and a non-inverting input coupled to the second PD cell phase error output.
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公开(公告)号:US20220224343A1
公开(公告)日:2022-07-14
申请号:US17461996
申请日:2021-08-31
Applicant: Texas Instruments Incorporated
Inventor: Michael Henderson Perrott , Robert Karl Butler
Abstract: In described examples, a phase locked loop (PLL) has a first phase detector cell (PD) that has a gain polarity. The first PD cell has a phase error output and inputs coupled to a reference frequency signal and a feedback signal. A second PD cell has an opposite gain polarity. The second PD cell has a phase error output and inputs coupled to the reference frequency signal and the feedback signal. A loop filter has a feedforward path and a (lossy) integrating path coupled to an output of the filter. The feedforward path has a third PD cell that has phase error output AC-coupled to the filter output. The integrating path includes an opamp that has an inverting input coupled to the first PD cell phase error output and a non-inverting input coupled to the second PD cell phase error output.
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公开(公告)号:US12218672B2
公开(公告)日:2025-02-04
申请号:US18092091
申请日:2022-12-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Michael Henderson Perrott
Abstract: In some examples, an apparatus includes a delay-based frequency multiplier and an error detection circuit. The delay-based frequency multiplier has a clock input, a multiplier clock output, and a delay calibration input. The error detection circuit has a detection input and a detection output. The detection input is coupled to the multiplier clock output, and the detection output is coupled to the delay calibration input. The error detection circuit is configured to receive a clock signal at the detection input, and provide a period error signal at the detection output based on a time difference between a first edge of the clock signal and a second edge of a delayed version of the clock signal.
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公开(公告)号:US20240146311A1
公开(公告)日:2024-05-02
申请号:US18404055
申请日:2024-01-04
Applicant: Texas Instruments Incorporated
Inventor: Michael Henderson Perrott , Hon Kin Chiu
IPC: H03L7/08 , G11C11/4093 , G11C11/4099 , H03L7/04 , H03L7/081 , H03L7/107 , H03L7/187 , H03M1/06 , H03M1/08 , H03M1/18
CPC classification number: H03L7/0807 , G11C11/4093 , G11C11/4099 , H03L7/04 , H03L7/0816 , H03L7/1072 , H03L7/187 , H03M1/0626 , H03M1/0687 , H03M1/0836 , H03M1/182
Abstract: In described examples, an apparatus comprises a multi-modulus divider (MMD) having a divider input, a divisor input, and a divider output. The apparatus also comprises a phase detector (PD) having a first clock input, a second clock input, and a PD output, the second clock input coupled to the divider output. The apparatus also comprises a phase to digital converter (P2DC) having a P2DC input and a P2DC output, the P2DC input coupled to the PD output. The apparatus further comprises a delta-sigma modulator having a third clock input, a modulator input, and a modulator output, the third clock input coupled to the divider output, the modulator input coupled to the P2DC output, and the modulator output coupled to the divisor input.
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公开(公告)号:US12224708B2
公开(公告)日:2025-02-11
申请号:US17389935
申请日:2021-07-30
Applicant: Texas Instruments Incorporated
Inventor: Bichoy Bahr , Michael Henderson Perrott , Baher Haroun , Swaminathan Sankaran
Abstract: An oscillator circuit includes a first BAW oscillator, a first coupling stage, a second BAW oscillator, and a second coupling stage. The first BAW oscillator is configured to generate a first output signal at a frequency. The first coupling stage is coupled to the first BAW oscillator, and is configured to amplify the first output signal. The second BAW oscillator is coupled to the first coupling stage, and is configured to generate a second output signal at the frequency. The second output signal differs in phase from the first output signal. The second coupling stage is coupled to the first BAW oscillator and the second BAW oscillator, and is configured to amplify the second output signal and drive the first BAW oscillator.
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公开(公告)号:US12132465B2
公开(公告)日:2024-10-29
申请号:US17537776
申请日:2021-11-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Jeronimo Segovia-Fernandez , Bichoy Bahr , Ting-Ta Yen , Michael Henderson Perrott , Zachary Schaffer
CPC classification number: H03H9/175 , H03H9/02015 , H03H9/131
Abstract: A tunable bulk acoustic wave (BAW) resonator includes: a first electrode adapted to be coupled to an oscillator circuit; a second electrode adapted to be coupled to the oscillator circuit; and a piezoelectric layer between the first electrode and the second electrode; and a Bragg mirror. The Bragg mirror has: a metal layer; and a dielectric layer between the metal layer and either of the first electrode or the second electrode. The tunable BAW resonator also includes: a radio-frequency (RF) signal source having a first end and a second end, the first end coupled to the first electrode, and the second end coupled to the second electrode; and an amplifier circuit between either the first electrode or the second electrode and the Bragg mirror metal layer.
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公开(公告)号:US20240039542A1
公开(公告)日:2024-02-01
申请号:US18482925
申请日:2023-10-09
Applicant: Texas Instruments Incorporated
Inventor: Michael Henderson Perrott , Robert Karl Butler
IPC: H03L7/08 , H03L7/107 , H03L7/081 , H03L7/187 , H03L7/04 , G11C11/4093 , G11C11/4099 , H03M1/06 , H03M1/08 , H03M1/18
CPC classification number: H03L7/0807 , H03L7/1072 , H03L7/0816 , H03L7/187 , H03L7/04 , G11C11/4093 , G11C11/4099 , H03M1/0626 , H03M1/0687 , H03M1/0836 , H03M1/182
Abstract: In described examples, a phase measurement circuit includes a first switch coupled between a power terminal and a phase measurement output, the first switch having a first switch control terminal coupled to an up input. The phase measurement circuit includes a second switch coupled between the phase measurement output, the second switch having a second switch control terminal coupled to a down input. The phase measurement circuit includes a first capacitor coupled between the power terminal and the phase measurement output, a second capacitor coupled between the phase measurement output and a ground terminal, and a charge pump circuit having a first control input, a second control input, and a charge pump output, the first control input coupled to the up input, the second control input coupled to the down input, and the charge pump output coupled to the phase measurement output.
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