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公开(公告)号：US20240250688A1
公开(公告)日：2024-07-25
申请号：US18158662
申请日：2023-01-24
Applicant: QUALCOMM Incorporated
CPC classification number: H03L7/187 , H03L7/093 , H03L7/0992
Abstract: A clock recovery circuit includes a frequency tracking loop including a first charge pump, and a phase tracking loop including a second charge pump. A voltage-controlled oscillator responds to the frequency tracking loop in a first operating mode and to the phase tracking loop in a second operating mode. A lock detector outputs an activation signal that indicates whether the clock recovery circuit has acquired frequency lock. A loop filter coupled to an input of the voltage-controlled oscillator includes a switchable resistor and a programmable delay element responsive to the activation signal. The first charge pump is disabled when the activation signal indicates frequency lock has been acquired, and disabled when the activation signal indicates frequency lock has not been acquired. The switchable resistor is bypassed when an output of the programmable delay element is in the first signaling state.
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公开(公告)号：US11989049B2
公开(公告)日：2024-05-21
申请号：US17487214
申请日：2021-09-28
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Jichao Huang , Qing Min , Lei Lu
CPC classification number: G06F1/08 , H03B5/1228 , H03L7/0991 , H03L7/187
Abstract: An oscillator and a clock circuit are disclosed. In an oscillator (100), a tail inductor connected to a cross-coupled transistor includes at least two inductors connected in parallel. Therefore, an inductance of the tail inductor is less than an inductance of any one of the inductors. This can address a design difficulty that a tail inductor with a smaller inductance needs to be used as an operating frequency of a VCO increases. The oscillator (100) includes a first cross-coupled transistor (121) and a first tail inductor (111). The first tail inductor (111) includes at least two inductors connected in parallel. The first tail inductor (111) is coupled to a source of the first cross-coupled transistor (121). The source of the first cross-coupled transistor (121) is coupled to a power supply or a ground through the first tail inductor (111).
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公开(公告)号：US20240039542A1
公开(公告)日：2024-02-01
申请号：US18482925
申请日：2023-10-09
Applicant: Texas Instruments Incorporated
Inventor： Michael Henderson Perrott , Robert Karl Butler
IPC: H03L7/08 , H03L7/107 , H03L7/081 , H03L7/187 , H03L7/04 , G11C11/4093 , G11C11/4099 , H03M1/06 , H03M1/08 , H03M1/18
CPC classification number: H03L7/0807 , H03L7/1072 , H03L7/0816 , H03L7/187 , H03L7/04 , G11C11/4093 , G11C11/4099 , H03M1/0626 , H03M1/0687 , H03M1/0836 , H03M1/182
Abstract: In described examples, a phase measurement circuit includes a first switch coupled between a power terminal and a phase measurement output, the first switch having a first switch control terminal coupled to an up input. The phase measurement circuit includes a second switch coupled between the phase measurement output, the second switch having a second switch control terminal coupled to a down input. The phase measurement circuit includes a first capacitor coupled between the power terminal and the phase measurement output, a second capacitor coupled between the phase measurement output and a ground terminal, and a charge pump circuit having a first control input, a second control input, and a charge pump output, the first control input coupled to the up input, the second control input coupled to the down input, and the charge pump output coupled to the phase measurement output.
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4.发明授权公开(公告)号：US09461657B2
公开(公告)日：2016-10-04
申请号：US14566847
申请日：2014-12-11
Applicant: QUALCOMM Incorporated
Inventor： Ian Galton
CPC classification number: H03L7/093 , H03L7/0991 , H03L7/187 , H03L7/197
Abstract: Certain aspects of the present disclosure support a method and apparatus for foreground and background bandwidth calibration in a frequency-do-digital converter based phase-locked loop (FDC-PLL) device.
Abstract translation: 本公开的某些方面支持用于基于频率 - 数字转换器的锁相环（FDC-PLL）装置中的前景和背景带宽校准的方法和装置。
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公开(公告)号：US09350363B2
公开(公告)日：2016-05-24
申请号：US14475393
申请日：2014-09-02
Applicant: KABUSHIKI KAISHA TOSHIBA
Inventor： Takashi Tokairin , Hideaki Masuoka
Abstract: According to one embodiment, a voltage-controlled oscillation (VCO) circuit includes a current source, an oscillation core unit, an amplitude detection unit, a current control unit, a low pass filter, and a switch. The current source supplies a bias current to the oscillation core unit in accordance with a current control signal. The oscillation core unit oscillates according to the bias current and outputs an oscillation signal. The amplitude detection unit outputs a detection voltage according to an amplitude of the oscillation signal. The current control unit outputs a control signal so that the detection voltage is equal to a reference voltage. The low pass filter generates the current control signal by filtering the control signal, and then supplies the current control signal to the current source. The switch is connected in parallel with the low pass filter.
Abstract translation: 根据一个实施例，压控振荡（VCO）电路包括电流源，振荡核心单元，振幅检测单元，电流控制单元，低通滤波器和开关。 电流源根据电流控制信号向振荡核心单元提供偏置电流。 振荡核心单元根据偏置电流进行振荡并输出振荡信号。 振幅检测单元根据振荡信号的振幅输出检测电压。 电流控制单元输出控制信号，使得检测电压等于参考电压。 低通滤波器通过滤波控制信号产生电流控制信号，然后将电流控制信号提供给电流源。 开关与低通滤波器并联连接。
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Patent Agency Ranking
公开(公告)号：US20150326233A1
公开(公告)日：2015-11-12
申请号：US14697465
申请日：2015-04-27
Applicant: Skyworks Solutions, Inc.
Inventor： Hua Wang , David Steven Ripley , Bryan J. Roll
IPC: H03L7/099
Abstract: Apparatus and methods for tuning a voltage controlled oscillator (VCO) are provided. In one aspect, a method of auto-tuning in a phase-locked loop includes generating a VCO clock signal using a VCO coupled to a capacitor array, dividing the VCO clock signal to generate a divided clock signal using a prescaler circuit having a selectable division ratio, controlling a value of the selectable division ratio using a first counter and a second counter of a counter module, generating a phase-frequency detector feedback signal based on a division control signal M and the divided clock signal using the counter module, counting a number of cycles of the divided clock signal that occur during a calibration interval using a cycle counter of a digital processing logic circuit, and determining the value of a capacitor array control signal based on the number of cycles counted during the calibration interval.
Abstract translation: 提供了用于调谐压控振荡器（VCO）的装置和方法。 一方面，一种在锁相环路中进行自整定的方法包括使用耦合到电容器阵列的VCO来产生VCO时钟信号，使用具有可选择划分的预分频器电路分频VCO时钟信号以产生分频时钟信号 使用计数器模块的第一计数器和第二计数器来控制可选分频比的值，使用计数器模块生成基于分割控制信号M的相位频率检测器反馈信号和分频时钟信号，计数一个 使用数字处理逻辑电路的周期计数器在校准间隔期间发生的划分的时钟信号的周期数，以及基于在校准间隔期间计数的周期数来确定电容器阵列控制信号的值。
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公开(公告)号：US20140091864A1
公开(公告)日：2014-04-03
申请号：US14101094
申请日：2013-12-09
Applicant: SKYWORKS SOLUTIONS, INC.
Inventor： Hua Wang , David Steven Ripley , Bryan J. Roll
IPC: H03L7/18
Abstract: Apparatus and methods for tuning a voltage controlled oscillator (VCO) are provided. In one aspect, a method of auto-tuning in a phase-locked loop includes generating a VCO clock signal using a VCO coupled to a capacitor array, dividing the VCO clock signal to generate a divided clock signal using a prescaler circuit having a selectable division ratio, controlling a value of the selectable division ratio using a first counter and a second counter of a counter module, generating a phase-frequency detector feedback signal based on a division control signal M and the divided clock signal using the counter module, counting a number of cycles of the divided clock signal that occur during a calibration interval using a cycle counter of a digital processing logic circuit, and determining the value of a capacitor array control signal based on the number of cycles counted during the calibration interval.
Abstract translation: 提供了用于调谐压控振荡器（VCO）的装置和方法。 一方面，一种在锁相环路中进行自整定的方法包括使用耦合到电容器阵列的VCO来产生VCO时钟信号，使用具有可选择划分的预分频器电路分频VCO时钟信号以产生分频时钟信号 比例，使用计数器模块的第一计数器和第二计数器控制可选分频比的值，使用计数器模块生成基于分割控制信号M的相位频率检测器反馈信号和分频时钟信号，计数一个 使用数字处理逻辑电路的周期计数器在校准间隔期间发生的划分的时钟信号的周期数，以及基于在校准间隔期间计数的周期数来确定电容器阵列控制信号的值。
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8.发明授权Phase locked loop circuit including automatic frequency control circuit and operating method thereof 有权包括自动频率控制电路的锁相环电路及其操作方法公开(公告)号：US08350608B2
公开(公告)日：2013-01-08
申请号：US12976449
申请日：2010-12-22
Applicant: Hui Dong Lee , Seok Ju Yun , Kwi Dong Kim , Jong-Kee Kwon , Sang-Hyun Cho
Inventor： Hui Dong Lee , Seok Ju Yun , Kwi Dong Kim , Jong-Kee Kwon , Sang-Hyun Cho
IPC: H03L7/06
CPC classification number: H03L7/083 , H03J2200/10 , H03L7/0891 , H03L7/0995 , H03L7/187
Abstract: Provided is a PLL circuit including automatic frequency control circuit and an operating method thereof. The voltage controlled oscillator is primarily controlled by an automatic frequency control circuit, and is secondarily controlled by a loop filter. The voltage controlled oscillator outputs a coarsely-tuned oscillation signal when primarily controlled, and outputs a finely-tuned oscillation signal when secondarily controlled. The PLL circuit can have a quick frequency fixing time, and output the oscillation signal having a broad and stable frequency. Moreover, the noise characteristic of the PLL circuit is enhanced.
Abstract translation: 提供一种包括自动频率控制电路的PLL电路及其操作方法。 压控振荡器主要由自动频率控制电路控制，二次由环路滤波器控制。 压控振荡器在主要受控时输出粗调谐振荡信号，并在二次控制时输出微调振荡信号。 PLL电路可以具有快速的频率固定时间，并输出具有宽而稳定频率的振荡信号。 此外，提高了PLL电路的噪声特性。
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公开(公告)号：US08233577B1
公开(公告)日：2012-07-31
申请号：US12555237
申请日：2009-09-08
Applicant: Kerry Veenstra , Krishna Rangasayee , Robert Bielby
Inventor： Kerry Veenstra , Krishna Rangasayee , Robert Bielby
CPC classification number: H03L7/187 , H03K19/17736 , H03K19/17744 , H03K19/17784 , H04L25/0272 , H04L25/0282
Abstract: A signal routing apparatus comprises a register bank to store a set of data signals. A delay locked loop generates a set of phase displaced clock signals. A phase controlled read circuit sequentially routes the set of data signals from the register bank in response to the phase displaced clock signals. A Low Voltage Differential Signaling buffer connected to the phase controlled read circuit transmits the data signals in a Low Voltage Differential Signaling mode. The phase displaced clock signals operate in lieu of a higher clock rate in order to reduce power consumption.
Abstract translation: 信号路由装置包括用于存储一组数据信号的寄存器组。 延迟锁定环产生一组相移位时钟信号。 相位控制的读取电路响应于相移位的时钟信号顺序地将来自寄存器组的数据信号组传送。 连接到相位控制读取电路的低压差分信号缓冲器以低电压差分信号传输数据信号。 相移位的时钟信号代替更高的时钟频率，以便降低功耗。
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公开(公告)号：US08102215B2
公开(公告)日：2012-01-24
申请号：US11575214
申请日：2005-08-30
Applicant: Winfrid Birth
Inventor： Winfrid Birth
IPC: H03L7/10
CPC classification number: H03L7/187 , H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/0975 , H03L7/093 , H03L7/18
Abstract: The invention relates to a compensation method and phase-locked loop (PLL) circuit, wherein different kinds of two-point modulations are used and the integral regulator of a loop filter is replaced by introducing predetermined settings at the loop filter or at a voltage controlled oscillator. Thereby, the dynamic settling time of the PLL circuit can be improved to gain time for other circuit components which can thus assure required precision for the modulation.
Abstract translation: 本发明涉及一种补偿方法和锁相环（PLL）电路，其中使用不同种类的两点调制，并且通过在环路滤波器处或在电压控制下引入预定的设置来替代环路滤波器的积分调节器 振荡器 由此，可以提高PLL电路的动态建立时间，以获得其它电路部件的时间，从而可以确保调制所需的精度。
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