-
公开(公告)号：US20240348256A1
公开(公告)日：2024-10-17
申请号：US18753394
申请日：2024-06-25
发明人： Tsung-Hsien Tsai , Jason Hsu , Ruey-Bin Sheen
CPC分类号： H03L7/0992 , H03L7/187
摘要： A tuning array selection circuit, together with a decoder and a voltage controlled oscillator (VCO), can be employed to overcome some disadvantages of previous methods of phase locked loops. For example, a VCO can include a coarse tuning array and a fine tuning array. A coarse tuning array can be used to tune a VCO to generate a signal within a wide frequency range. A fine tuning array can be used to tune a VCO to generate a signal within a narrow frequency range. In one embodiment, the narrow frequency range is within the wide frequency range. The tuning array selection circuit can coordinate selection of appropriate fine tuning devices and narrow tuning devices to reduce transition jitter and the risk of fail locking of phase locked loops.
-
公开(公告)号：US12107589B2
公开(公告)日：2024-10-01
申请号：US18066542
申请日：2022-12-15
摘要： An apparatus that measures elapsed time in digital systems with multiple clocks includes a vernier reference (VREF) configured to generate a reference counter signal with a numeric output and two reference clock signals. The apparatus also includes a plurality of synchronizer VPLLs configured to receive the reference counter signal and the two reference clock signals and generate a plurality of synchronized counters, each synchronized counter being co-linear with the reference counter and operating in a respective target clock domain.
-
公开(公告)号：US12052023B1
公开(公告)日：2024-07-30
申请号：US18158662
申请日：2023-01-24
CPC分类号： H03L7/187 , H03L7/093 , H03L7/0992
摘要： A clock recovery circuit includes a frequency tracking loop including a first charge pump, and a phase tracking loop including a second charge pump. A voltage-controlled oscillator responds to the frequency tracking loop in a first operating mode and to the phase tracking loop in a second operating mode. A lock detector outputs an activation signal that indicates whether the clock recovery circuit has acquired frequency lock. A loop filter coupled to an input of the voltage-controlled oscillator includes a switchable resistor and a programmable delay element responsive to the activation signal. The first charge pump is disabled when the activation signal indicates frequency lock has been acquired, and disabled when the activation signal indicates frequency lock has not been acquired. The switchable resistor is bypassed when an output of the programmable delay element is in the first signaling state.
-
公开(公告)号：US12046271B2
公开(公告)日：2024-07-23
申请号：US18509485
申请日：2023-11-15
发明人： Jingwei Cheng
CPC分类号： G11C11/4076 , G11C7/1093 , G11C7/222 , G11C29/023 , H03L7/093 , H03L7/0992
摘要： A clock system and a memory are disclosed. The clock system includes a system on chip (SoC) configured to generate a first oscillation signal, a second oscillation signal, a third oscillation signal and a fourth oscillation signal of a same frequency and amplitude. Further, the clock system includes a memory chip configured to output a data signal based on signal edges of the first oscillation signal, the second oscillation signal, the third oscillation signal and the fourth oscillation signal, and output a command/address signal based on the signal edges of the first oscillation signal and the third oscillation signal. The signal edges are rising edges or falling edges.
-
公开(公告)号：US12021542B2
公开(公告)日：2024-06-25
申请号：US17685676
申请日：2022-03-03
发明人： Maciej Jankowski , Ruediger Kuhn
CPC分类号： H03M1/0626 , H03L7/0992 , H03L7/18 , H03L7/23 , H03M1/127 , H03M1/0845
摘要： A device includes a voltage converter and an analog to digital converter (ADC). The voltage converter includes an input to receive a first voltage and an output to output a second voltage based on a switching signal having a first discrete converter frequency and a second discrete converter frequency. The ADC is coupled to and proximate to the voltage converter. The ADC includes a digital filter configured to substantially attenuate a first filter frequency and a second filter frequency. The voltage converter further includes a frequency control device configured to set the first discrete converter frequency and the second discrete converter frequency so that the first discrete converter frequency is approximately equal to the first filter frequency and the second discrete converter frequency is approximately equal to the second filter frequency.
-
公开(公告)号：US20240187007A1
公开(公告)日：2024-06-06
申请号：US18060856
申请日：2022-12-01
CPC分类号： H03L7/0994 , G06F1/0328 , H03L7/0992 , H03M1/12
摘要： A numerically controlled oscillator system for maintaining a consistent phase reference while switching data rates may include a numerically controlled oscillator (NCO) circuit. The NCO circuit may include a phase accumulator, a phase-to-signal mapping circuit, and a first free-running counter. The phase accumulator may receive a new phase value as an input in response to an update signal. The phase-to-signal mapping circuit may map a value from the phase accumulator to a periodic signal. The first free-running counter may continue counting, without being reset, while the numerically controlled oscillator system is switching digital data rates. The first free-running counter may be configured to provide the new phase value to the phase accumulator using a representation of a counter value of the first free-running counter and a frequency tuning word defined by a representation of a frequency of the periodic signal.
-
公开(公告)号：US11967933B2
公开(公告)日：2024-04-23
申请号：US17849484
申请日：2022-06-24
发明人： Gebhard Haug , Dirk Preikszat
CPC分类号： H03D11/06 , H03L7/0992 , H04L7/0012 , H04L25/0268
摘要： In an example, a system includes circuitry on a first side of an isolation barrier and circuitry on a second side of the isolation barrier, where the isolation barrier is operable to electrically isolate the first side from the second side. The system also includes a trimmed oscillator, a first transmitter, and a first receiver on the first side, the trimmed oscillator coupled to the first transmitter. The system includes a tunable oscillator, a second transmitter, and a second receiver on the second side, the tunable oscillator coupled to the second receiver and the second transmitter. In the system, the first side is configured to transmit a training sequence to the second side, and the second side is configured to tune the tunable oscillator based on the training sequence.
-
公开(公告)号：US11962315B2
公开(公告)日：2024-04-16
申请号：US17916200
申请日：2020-03-31
CPC分类号： H03L7/0992 , H03B5/1212 , H03L7/093 , H03B2201/0208
摘要： A phase-locked loop comprises a voltage controlled oscillator. The voltage controlled oscillator comprises an inductor and a capacitor, connected in parallel, and also connected in parallel therewith, a negative resistance structure. A first terminal of the negative resistance structure is connected to respective first terminals of the inductor and the capacitor. A second terminal of the negative resistance structure is connected to respective second terminals of the inductor and the capacitor. The negative resistance structure exhibits a tunable capacitance, such that a frequency of an output of the voltage controlled oscillator can be tuned by a control input signal, and the control input signal is generated in the phase-locked loop. The negative resistance structure comprises first and second transistors. There is a first conduction path between the first terminal of the first transistor and the control terminal of the second transistor, and a second conduction path between the control terminal of the first transistor and the first terminal of the second transistor. The control terminal of at least one of the first and second transistors is biased by the control input signal, such that a parasitic capacitance of said at least one of the first and second transistors can be tuned by the control input signal, in order to tune the frequency of the output of the voltage controlled oscillator, and hence the frequency of oscillation of the phase-locked loop.
-
公开(公告)号：US20240106422A1
公开(公告)日：2024-03-28
申请号：US17954126
申请日：2022-09-27
IPC分类号： H03K3/0231 , H03B5/04 , H03B5/24 , H03K3/03 , H03L7/099
CPC分类号： H03K3/0231 , H03B5/04 , H03B5/24 , H03K3/0315 , H03L7/0992 , H03L7/0995
摘要： One or more devices, systems, and/or methods are provided. In an example of the techniques presented herein, an oscillator comprises a voltage controlled oscillator configured to generate an output clock based on a drive signal, a frequency to voltage converter having a time constant and configured to generate a feedback voltage having a decay cycle based on the time constant and a frequency based on a frequency of the output clock, and an integrator configured to generate the drive signal based on an integration of the feedback voltage and a reference voltage.
-
公开(公告)号：US20240048144A1
公开(公告)日：2024-02-08
申请号：US18352581
申请日：2023-07-14
CPC分类号： H03L7/0814 , H03L7/0992
摘要： A device includes a local oscillator, an all-digital phase-locked loop, a digital signal generator, sampling circuitry, and an interface. The local oscillator generates a local clock signal. The all-digital phase locked loop generates a sampling control signal. The ADPLL includes a phase-error detector, a digital filter and a sigma-delta modulator. The phase detector generates a phase error signal based on a loop clock signal and a received reference signal. The digital filter generates a signal indicative of a frequency ratio between a frequency of the reference clock signal and the local clock frequency based on the phase error signal. The sigma-delta modulator generates a modulated signal based on the signal indicative of the frequency ratio. The sampling control signal is based on the modulated signal. The sampling circuitry samples digital signals generated by the digital signal generator at a sampling frequency, which is a function of the sampling control signal.
-
-
-
-
-
-
-
-
-
搜索结果
552 条记录 (耗时 0.026 秒)
