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公开(公告)号：US20240250688A1
公开(公告)日：2024-07-25
申请号：US18158662
申请日：2023-01-24
Applicant: QUALCOMM Incorporated
CPC classification number: H03L7/187 , H03L7/093 , H03L7/0992
Abstract: A clock recovery circuit includes a frequency tracking loop including a first charge pump, and a phase tracking loop including a second charge pump. A voltage-controlled oscillator responds to the frequency tracking loop in a first operating mode and to the phase tracking loop in a second operating mode. A lock detector outputs an activation signal that indicates whether the clock recovery circuit has acquired frequency lock. A loop filter coupled to an input of the voltage-controlled oscillator includes a switchable resistor and a programmable delay element responsive to the activation signal. The first charge pump is disabled when the activation signal indicates frequency lock has been acquired, and disabled when the activation signal indicates frequency lock has not been acquired. The switchable resistor is bypassed when an output of the programmable delay element is in the first signaling state.
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公开(公告)号：US11989049B2
公开(公告)日：2024-05-21
申请号：US17487214
申请日：2021-09-28
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Jichao Huang , Qing Min , Lei Lu
CPC classification number: G06F1/08 , H03B5/1228 , H03L7/0991 , H03L7/187
Abstract: An oscillator and a clock circuit are disclosed. In an oscillator (100), a tail inductor connected to a cross-coupled transistor includes at least two inductors connected in parallel. Therefore, an inductance of the tail inductor is less than an inductance of any one of the inductors. This can address a design difficulty that a tail inductor with a smaller inductance needs to be used as an operating frequency of a VCO increases. The oscillator (100) includes a first cross-coupled transistor (121) and a first tail inductor (111). The first tail inductor (111) includes at least two inductors connected in parallel. The first tail inductor (111) is coupled to a source of the first cross-coupled transistor (121). The source of the first cross-coupled transistor (121) is coupled to a power supply or a ground through the first tail inductor (111).
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公开(公告)号：US20240039542A1
公开(公告)日：2024-02-01
申请号：US18482925
申请日：2023-10-09
Applicant: Texas Instruments Incorporated
Inventor： Michael Henderson Perrott , Robert Karl Butler
IPC: H03L7/08 , H03L7/107 , H03L7/081 , H03L7/187 , H03L7/04 , G11C11/4093 , G11C11/4099 , H03M1/06 , H03M1/08 , H03M1/18
CPC classification number: H03L7/0807 , H03L7/1072 , H03L7/0816 , H03L7/187 , H03L7/04 , G11C11/4093 , G11C11/4099 , H03M1/0626 , H03M1/0687 , H03M1/0836 , H03M1/182
Abstract: In described examples, a phase measurement circuit includes a first switch coupled between a power terminal and a phase measurement output, the first switch having a first switch control terminal coupled to an up input. The phase measurement circuit includes a second switch coupled between the phase measurement output, the second switch having a second switch control terminal coupled to a down input. The phase measurement circuit includes a first capacitor coupled between the power terminal and the phase measurement output, a second capacitor coupled between the phase measurement output and a ground terminal, and a charge pump circuit having a first control input, a second control input, and a charge pump output, the first control input coupled to the up input, the second control input coupled to the down input, and the charge pump output coupled to the phase measurement output.
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公开(公告)号：US11569824B2
公开(公告)日：2023-01-31
申请号：US17344390
申请日：2021-06-10
Applicant: Arm Limited
Inventor： Shidhartha Das , Yunpeng Cai , Supreet Jeloka
Abstract: Various implementations described herein are directed to a device with a voltage-controlled oscillator that receives an enable signal, receives a reset signal, and provides internal pulse signals including one or more coarse internal pulse signals and multiple fine internal pulse signals. The device may have a coarse sampler that receives the one or more coarse internal pulse signal and provides a coarse sampled output signal. The device may have a fine sampler that receives the multiple fine internal pulse signals and provides a fine sampled output signal.
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公开(公告)号：US20230008340A1
公开(公告)日：2023-01-12
申请号：US17572690
申请日：2022-01-11
Inventor： Tsung-Hsien Tsai , Jason Hsu , Ruey-Bin Sheen
Abstract: A tuning array selection circuit, together with a decoder and a voltage controlled oscillator (VCO), can be employed to overcome some disadvantages of previous methods of phase locked loops. For example, a VCO can include a coarse tuning array and a fine tuning array. A coarse tuning array can be used to tune a VCO to generate a signal within a wide frequency range. A fine tuning array can be used to tune a VCO to generate a signal within a narrow frequency range. In one embodiment, the narrow frequency range is within the wide frequency range. The tuning array selection circuit can coordinate selection of appropriate fine tuning devices and narrow tuning devices to reduce transition jitter and the risk of fail locking of phase locked loops.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20220376694A1
公开(公告)日：2022-11-24
申请号：US17878042
申请日：2022-07-31
Applicant: Silicon Motion, Inc.
Inventor： Fu-Jen Shih
Abstract: A method and apparatus for performing on-system phase-locked loop (PLL) management in a memory device are provided. The method may include: utilizing a processing circuit within the memory controller to set multiple control parameters among multiple parameters stored in a register circuit of a transmission interface circuit within the memory controller, for controlling parameter adjustment of a PLL of the transmission interface circuit; utilizing a trimming control circuit to perform the parameter adjustment of the PLL according to the multiple control parameters, to adjust a set of voltage parameters among the multiple parameters, for optimizing a control voltage of a voltage controlled oscillator (VCO); and during the parameter adjustment of the PLL, utilizing the trimming control circuit to generate and store multiple processing results in the register circuit, for being sent back to the processing circuit, to complete the parameter adjustment of the PLL, thereby achieving the on-system PLL management.
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公开(公告)号：US20220271761A1
公开(公告)日：2022-08-25
申请号：US17678319
申请日：2022-02-23
Applicant: Morse Micro Pty. LTD.
Inventor： Yingbo Zhu
Abstract: The present disclosure is directed to a digital phase-locked loop frequency synthesizer including: a digitally controlled voltage-controlled oscillator (DCO); a reference oscillator; a digital phase detector; a DCO control module comprising a plurality of registers each arranged to control the frequency of the signal with a predetermined resolution; a first feedback loop arranged to provide a first feedback path between the output of the DCO and the digital phase detector; and a second feedback loop arranged to provide a second feedback path between the first register output and the second register input, the second feedback loop comprising an adder module arranged to change a value of the second register based on the first register output to maximize a DCO frequency output range provided by the first register.
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公开(公告)号：US20210036709A1
公开(公告)日：2021-02-04
申请号：US16964369
申请日：2019-01-31
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seungjoon YOON , Cheolho LEE
Abstract: An integrated circuit according to an embodiment of the disclosure may include a plurality of function blocks, a spread spectrum clock (SSC) generator that generates a spread spectrum clock based on a frequency modulation rate value, a clock distribution circuit that distributes the generated spread spectrum clock into the plurality of function blocks, a memory that stores predetermined frequency modulation rate values respectively corresponding to the plurality of function blocks, and a control circuit, and the control circuit may be configured to generate the spread spectrum clock based on a smaller frequency modulation rate value among a first frequency modulation rate value and a second frequency modulation rate value respectively corresponding to a first function block and a second function block, which are operating, from among the plurality of function blocks. Moreover, various embodiment found through the present disclosure are possible.
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公开(公告)号：US10715158B1
公开(公告)日：2020-07-14
申请号：US16424365
申请日：2019-05-28
Applicant: Synopsys, Inc.
Inventor： Akarsh Joshi , Sharath Nadsar , Biman Chattopadhyay
Abstract: A phase-locked loop (PLL) for generating a VCO output signal at a target frequency has been disclosed. The PLL includes at least first and second VCOs, first and second multiplexers, and a frequency divider. The first and second VCOs generate first and second output signals over first and second frequency ranges, respectively. The first multiplexer receives the first and second output signals from the first and second VCOs, respectively, and outputs the first output signal when the target frequency is in the first frequency range and the second output signal when the target frequency is in the second frequency range or less than the first frequency range. The frequency divider divides a frequency of the second output signal by a division factor to generate a third output signal. The second multiplexer outputs one of the first, second, and third output signals as the VCO output signal.
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公开(公告)号：US20200218298A1
公开(公告)日：2020-07-09
申请号：US16792128
申请日：2020-02-14
Applicant: Power Integrations, Inc.
Inventor： Giao Minh Pham , Lance M. Wong
Abstract: A controller for use in a power converter including a jitter generator circuit coupled to receive a drive signal from a switch controller and generate a jitter signal. The jitter signal is a modulated jitter signal when the drive signal is below a first threshold frequency. The switch controller is coupled to a power switch coupled to an energy transfer element. The switch controller is coupled to receive a current sense signal representative of a current through the power switch. The switch controller is coupled to generate the drive signal to control switching of the power switch in response to the current sense signal and the jitter signal to control a transfer of energy from an input of the power converter to an output of the power converter.
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