公开(公告)号：US20230336183A1

公开(公告)日：2023-10-19

申请号：US18186657

申请日：2023-03-20

申请人： NetApp Inc.

发明人： Ram Kesavan ,  Matthew Fontaine Curtis-Maury ,  Abdul Basit ,  Vinay Devadas ,  Ananthan Subramanian ,  Mark Smith

IPC分类号： H03M1/06 ,  G06F3/06 ,  G06F16/901

CPC分类号： H03M1/0687 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0685 ,  G06F16/9027 ,  H03M1/0695

摘要： Techniques are provided for implementing a file system format for persistent memory. A node, comprising persistent memory, receives an operation comprising a file identifier and file system instance information. A list of file system info objects are evaluated to identify a file system info object matching the file system instance information. An inofile, identified by the file system info object as being associated with inodes of files within an instance of the file system targeted by the operation, is traversed to identify an inode matching the file identifier. If the inode comprises an indicator that the file is tiered into the persistent memory, then the inode it utilized to facilitate execution of the operation upon the persistent memory. Otherwise, the operation is routed to a storage file system tier for execution by a storage file system upon storage associated with the node.

公开(公告)号：US09013345B2

公开(公告)日：2015-04-21

申请号：US14161790

申请日：2014-01-23

申请人： Tomoki Segawa ,  Fumihiro Inoue

发明人： Tomoki Segawa ,  Fumihiro Inoue

IPC分类号： H03M1/12 ,  H03M1/06 ,  H03M1/40

CPC分类号： H03M1/1245 ,  H03M1/0687 ,  H03M1/0697 ,  H03M1/40

摘要： A successive approximation AD converter includes a DA converter that converts a higher conversion data greater than an approximate value into an analog higher converted voltage and converts a lower conversion data less than the approximate value into an analog lower converted voltage; a sample-and-hold circuit that samples and holds voltage differences between an input voltage and each of the higher converted voltage and the lower converted voltage; a comparator that outputs a first comparison result indicating whether the input voltage is greater or less than the higher converted voltage and a second comparison result indicating whether the input voltage is greater or less than the lower converted voltage; and an operation unit that changes the approximate value based on the first comparison result and the second comparison result, and changes a next higher conversion data and a next lower conversion data based on the changed approximate value.

摘要翻译： 逐次逼近AD转换器包括DA转换器，其将大于近似值的较高转换数据转换为模拟更高转换电压，并将小于近似值的较低转换数据转换为模拟较低转换电压; 采样和保持电路，其对输入电压和较高转换电压和较低转换电压之间的电压差进行采样和保持; 输出表示所述输入电压是大于还是小于所述较高转换电压的第一比较结果的比较器，以及指示所述输入电压是否大于或小于所述较低转换电压的第二比较结果; 以及基于第一比较结果和第二比较结果改变近似值的操作单元，并且基于改变的近似值来改变下一较高转换数据和下一较低转换数据。

公开(公告)号：US20130106628A1

公开(公告)日：2013-05-02

申请号：US13282262

申请日：2011-10-26

申请人： John Earle Miller ,  Robert Floyd Payne

发明人： John Earle Miller ,  Robert Floyd Payne

IPC分类号： H03M1/38 ,  H03M1/06

CPC分类号： H03M1/0687 ,  H03M1/167

摘要： An analog-to-digital converter (ADC) function in which digital error correction is provided. Parallel ADC stages are synchronously clocked to convert an analog input signal into digital words; at least one of the digital outputs is encoded according to an error correction code. Decision logic circuitry decodes a code word comprised of the concatenation of the digital outputs from the parallel stages, to derive a digital output from which the digital output word corresponding to the analog input signal can be derived. The decision logic circuitry can provide an error signal used to correct the state of one or more bits of the digital output from one of the ADC stages, for the case of a systematic code; alternatively, the decision logic circuitry can directly decode the code word to provide the digital output. The architecture may be applied to stages in a pipelined ADC.

摘要翻译： 提供数字纠错的模数转换器（ADC）功能。 并行ADC级同步计时，将模拟输入信号转换为数字字; 数字输出中的至少一个根据纠错码进行编码。 判决逻辑电路对由并行级的数字输出的级联组成的代码字进行解码，以导出数字输出，从该数字输出可以导出与模拟输入信号对应的数字输出字。 对于系统代码的情况，判决逻辑电路可以提供用于校正来自ADC级之一的数字输出的一个或多个位的状态的误差信号; 或者，判决逻辑电路可以直接解码码字以提供数字输出。 该架构可以应用于流水线ADC中的阶段。

公开(公告)号：US06847242B2

公开(公告)日：2005-01-25

申请号：US10825204

申请日：2004-04-16

申请人： In-Young Chung

发明人： In-Young Chung

IPC分类号： H03M1/68 ,  G11C7/16 ,  G11C7/22 ,  H03L7/081 ,  H03L7/089 ,  H03M1/06 ,  H03M1/08 ,  H03M1/66 ,  H03M1/74 ,  H03M7/00 ,  H03L7/06

CPC分类号： H03M1/0687 ,  G11C7/16 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0812 ,  H03L7/089 ,  H03M1/0863 ,  H03M1/664 ,  H03M1/745

摘要： A delay-locked loop (DLL) may include: a variable delay line arrangement operable to receive a reference clock and to output a delayed local clock; a phase comparator device operable to compare said reference clock and said local clock and to provide an up/down indication; and a delay control circuit, responsive to said up/down count-indication, to provide a reduced-noise delay control signal to said variable delay line arrangement, said delay control circuit being operable to count said up/down indication using an escalator code arrangement.

摘要翻译： 延迟锁定环（DLL）可以包括：可变延迟线布置，其可操作以接收参考时钟并输出延迟的本地时钟; 相位比较器装置，可操作以比较所述参考时钟和所述本地时钟并提供上/下指示; 以及延迟控制电路，响应于所述向上/向下计数指示，向所述可变延迟线装置提供降噪噪声延迟控制信号，所述延迟控制电路可操作以使用自动扶梯代码排列来计数所述上/下指示 。

公开(公告)号：US06778114B2

公开(公告)日：2004-08-17

申请号：US10251873

申请日：2002-09-23

申请人： In-Young Chung

发明人： In-Young Chung

IPC分类号： H03M166

CPC分类号： H03M1/0687 ,  G11C7/16 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0812 ,  H03L7/089 ,  H03M1/0863 ,  H03M1/664 ,  H03M1/745

摘要： A digital to analog converter (DAC) can comprise: an escalator code generator; and an escalator-code-to-analog converter (ECAC). The generator can (1) represent base 10 numbers with a mixed code having a coin code portion and a cash code portion, which will eliminate multi-bit changes in the cash code upon changes in count direction; and (2) represent a count in a first direction as the sum of the coin code and the cash code. The generator can alter the coin code when the count changes direction while the cash code remains the same until a count capacity of the coin code is exceeded, at which point the cash code can be altered. Cycling between adjacent base 10 numbers is absorbed by the coin code while keeping the cash code the same, which reduces noise introduced into an output of the ECAC due to such cycling.

摘要翻译： 数模转换器（DAC）可以包括：自动扶梯代码发生器; 和自动扶梯码模拟转换器（ECAC）。 发生器可以（1）代表具有硬币代码部分和现金代码部分的混合代码的基数10，这将在计数方向改变时消除现金代码中的多位变化; 和（2）表示作为硬币代码和现金代码的总和的第一方向的计数。 当计数改变方向时，发电机可以改变硬币代码，而现金代码保持相同，直到超过硬币代码的计数能力，此时可以更改现金代码。 相邻基数10之间的循环被硬币代码吸收，同时保持现金代码相同，这降低了由于这种循环引入到ECAC的输出中的噪声。

公开(公告)号：US06489914B1

公开(公告)日：2002-12-03

申请号：US10005275

申请日：2001-12-04

申请人： Robert S. Jones, III ,  Brett J. Thompsen

发明人： Robert S. Jones, III ,  Brett J. Thompsen

IPC分类号： H03M110

CPC分类号： H03M1/1023 ,  H03M1/0687 ,  H03M1/403

摘要： A RSD analog to digital converter has an RSD stage that in turn has a switched capacitor integrator (SCI). The SCI uses an operational amplifier. A capacitor, which operates as a offset compensation capacitor, is precharged to the offset voltage of the operational amplifier during a precharge phase. The next phase switches this offset compensation capacitor in the path of the capacitors which are used to perform the integration. The effect is that the offset of the operational amplifier is corrected by the use of the compensation capacitor that had been precharged to the offset voltage during the previous phase.

摘要翻译： RSD模数转换器具有RSD级，其依次具有开关电容积分器（SCI）。 SCI使用运算放大器。 作为偏移补偿电容器工作的电容器在预充电阶段被预充电到运算放大器的偏移电压。 下一相将该偏移补偿电容器切换到用于执行积分的电容器的路径中。 效果是通过使用在前一阶段预充电到偏移电压的补偿电容来校正运算放大器的偏移。

公开(公告)号：US06298459B1

公开(公告)日：2001-10-02

申请号：US09034219

申请日：1998-03-04

申请人： Sanroku Tsukamoto

发明人： Sanroku Tsukamoto

IPC分类号： G06F1100

CPC分类号： H03M1/0687 ,  H03M1/0809 ,  H03M1/1095 ,  H03M1/365 ,  H03M13/47

摘要： A high speed A/D converter includes a series of encoder sections for converting a thermometer code to a gray code and an error signal production section for detecting a babble error in the gray code and generating an error signal indicating such a babble error. An error correction section corrects babble errors in the gray code in response to the error signal. The corrected gray code is then converted to a binary code with a gray code to binary code converter. When the high speed A/D converter is incorporated in a semiconductor device, the A/D converter may be tested using a sampling clock having a phase which varies successively with respect to the input analog signal to sample the analog signal, and then evaluating the corresponding generated digital signal.

公开(公告)号：US11870446B2

公开(公告)日：2024-01-09

申请号：US17461997

申请日：2021-08-31

申请人： Texas Instruments Incorporated

发明人： Michael Henderson Perrott ,  Hon Kin Chiu

IPC分类号： H03M1/12 ,  H03L7/08 ,  H03L7/107 ,  H03L7/081 ,  H03L7/187 ,  H03L7/04 ,  G11C11/4093 ,  G11C11/4099 ,  H03M1/06 ,  H03M1/08 ,  H03M1/18

CPC分类号： H03L7/0807 ,  G11C11/4093 ,  G11C11/4099 ,  H03L7/04 ,  H03L7/0816 ,  H03L7/1072 ,  H03L7/187 ,  H03M1/0626 ,  H03M1/0687 ,  H03M1/0836 ,  H03M1/182

摘要： In described examples, a feedback loop has phase detection (PD) circuitry that has a reference input to receive a reference frequency signal, a feedback input to receive a feedback signal, and phase difference outputs. A phase to digital converter (P2DC) includes a first phase to charge converter (PCC) that has a gain polarity and a first phase error output; a second PCC that has an opposite gain polarity and a second phase error output. A differential loop filter has an amplifier with an inverting input coupled to the first phase error output and a non-inverting input coupled to the second phase error output. An analog to digital converter (ADC) has an input coupled to an output of the differential loop filter. A feedback path is coupled to the output of the P2DC, with an output of the feedback path providing the feedback signal to the PD feedback input.

公开(公告)号：US11784649B2

公开(公告)日：2023-10-10

申请号：US17461996

申请日：2021-08-31

申请人： Texas Instruments Incorporated

发明人： Michael Henderson Perrott ,  Robert Karl Butler

IPC分类号： H03L7/06 ,  H03L7/08 ,  H03L7/107 ,  H03L7/081 ,  H03L7/187 ,  H03L7/04 ,  G11C11/4093 ,  G11C11/4099 ,  H03M1/06 ,  H03M1/08 ,  H03M1/18

CPC分类号： H03L7/0807 ,  G11C11/4093 ,  G11C11/4099 ,  H03L7/04 ,  H03L7/0816 ,  H03L7/1072 ,  H03L7/187 ,  H03M1/0626 ,  H03M1/0687 ,  H03M1/0836 ,  H03M1/182

摘要： In described examples, a phase locked loop (PLL) has a first phase detector cell (PD) that has a gain polarity. The first PD cell has a phase error output and inputs coupled to a reference frequency signal and a feedback signal. A second PD cell has an opposite gain polarity. The second PD cell has a phase error output and inputs coupled to the reference frequency signal and the feedback signal. A loop filter has a feedforward path and a (lossy) integrating path coupled to an output of the filter. The feedforward path has a third PD cell that has phase error output AC-coupled to the filter output. The integrating path includes an opamp that has an inverting input coupled to the first PD cell phase error output and a non-inverting input coupled to the second PD cell phase error output.

公开(公告)号：US11658674B2

公开(公告)日：2023-05-23

申请号：US17501112

申请日：2021-10-14

申请人： STMicroelectronics S.r.l.

发明人： Nicola Errico ,  Marzia Annovazzi ,  Alessandro Cannone ,  Enrico Ferrara ,  Gea Donzelli ,  Paolo Turbanti

IPC分类号： H03M1/10 ,  H03M1/06

CPC分类号： H03M1/1071 ,  H03M1/0687

摘要： In an embodiment, a circuit includes N sensing channels. Each channel includes a first main sensing node and a second redundancy sensing node paired therewith. N analog-to-digital converters (ADCs) are coupled to the first sensing nodes, with digital processing circuits coupled to the N ADCs. A pair of multiplexers are coupled to the second sensing nodes and to the N ADCs with a further ADC coupled to the output of the second multiplexer. An error checking circuit is coupled to the outputs of the second multiplexer and the further ADC to compare, at each time window in a sequence of N time windows, a first digital value and a second digital value resulting from conversion to digital of: an analog sensing signal at one of the first sensing nodes, and an analog sensing signal at the second sensing node paired with the selected one of the first sensing nodes.