-
公开(公告)号：US20250167796A1
公开(公告)日：2025-05-22
申请号：US18839219
申请日：2022-02-24
Applicant: Telefonaktiebolaget LM Ericsson (publ)
Inventor： Mattias PALM , Martin ANDERSON , Pavel ANGELOV
Abstract: The present disclosure describes a time-interleaved current-steering digital to analog converter, TI-IDAC, having a first sub-DAC, a second sub-DAC, a load switch and an interleaving switch arranged between the sub-DACs and the load switch. The interleaving switch is configured to interleave between the sub-DACs by control of a connection between the first sub-DAC and an input port of the load switch, and control of a connection between the second sub-DAC and the input port of the load switch. Further to this, the load switch is configured such that the input port of the load switch is connected to a reset load of the TI-IDAC at least when the interleaving switch changes at least one of the connections between the sub-DACs and the input port of the load switch. Associated methods, electronic equipment, integrated circuits, computer programs and carriers are also disclosed.
-
公开(公告)号：US12301249B2
公开(公告)日：2025-05-13
申请号：US18310184
申请日：2023-05-01
Applicant: NXP B.V.
Inventor： Muhammed Bolatkale , Lucien Johannes Breems , Pierluigi Cenci , Shagun Bajoria , Mohammed Abo Alainein
Abstract: There is described an analog-to-digital converter, ADC, device (100), comprising: i) a first converter stage (110), comprising a first digital-to-analog converter, DAC, (115), comprising at least two first unit elements (116, 117, 118) each with a first unit element value (U11, U12, U13); ii) a second converter stage (120), comprising a second DAC (125), comprising at least two second unit elements each with a second unit element value (U21, U22, U23); and iii) a control device (180), coupled to the first DAC (115) and the second DAC and configured to: swap at least one of the first unit element values (U1) with at least one of the second unit element values (U2) to obtain corresponding third unit element values (U3) and forth unit element values (U4).
-
公开(公告)号：US12298798B2
公开(公告)日：2025-05-13
申请号：US18736150
申请日：2024-06-06
Applicant: pSemi Corporation
Inventor： Robert Mark Englekirk , Keith Bargroff , Christopher C. Murphy , Tero Tapio Ranta
Abstract: A controllable temperature coefficient bias (CTCB) circuit is disclosed. The CTCB circuit can provide a bias to an amplifier. The CTCB circuit includes a variable with temperature (VWT) circuit having a reference circuit and a control circuit. The control circuit has a control output, a first current control element and a second current control element. Each current control element has a “controllable” resistance. One of the two current control elements may have a relatively high temperature coefficient and another a relatively low temperature coefficient. A controllable resistance of one of the current control elements increases when the controllable resistance of the other current control element decreases. However, the “total resistance” of the current control circuit remains constant with a constant temperature. The VWT circuit has an output with a temperature coefficient that is determined by the relative amount of current that flows through each current control element of the control circuit. A Current Digital to Analog Converter (IDAC) scales the output of the VWT and provides the scaled output to an amplifier bias input.
-
公开(公告)号：US12289117B2
公开(公告)日：2025-04-29
申请号：US18083913
申请日：2022-12-19
Applicant: IMEC VZW , KATHOLIEKE UNIVERSITEIT LEUVEN
Inventor： Xiaohua Huang , Marco Ballini
Abstract: An input circuitry for receiving an analog input signal comprises: an input transistor configured to receive the analog input signal on a gate terminal of the input transistor wherein the input transistor is connected to a digital component providing a digital signal, and wherein the input transistor is configured to receive the digital signal on a bulk terminal of the input transistor; wherein the input transistor is configured to provide an output current based on the analog input signal and the digital signal, such that the input transistor provides digital-to-analog conversion of the digital signal received on the bulk terminal.
-
公开(公告)号：US12278019B2
公开(公告)日：2025-04-15
申请号：US18300203
申请日：2023-04-13
Applicant: Infineon Technologies Austria AG
Inventor： Jens Repp
Abstract: A device includes a plurality of digital-to-analog converters (DACs), a multiplexer, a plurality of electrodes including a first electrode, and a plurality of direct current (DC) offset circuits including a first DC offset circuit. At least one of the plurality of electrodes is located along a lane for movement of an ion. The multiplexer has multiple inputs coupled to the plurality of DACs and multiple outputs including a first output. The first output is configured to provide a first voltage. The first DC offset circuit is coupled between the first output and the first electrode. The first DC offset circuit is configured to add a first DC offset voltage to either the first voltage or the first voltage amplified by a first gain. The first DC offset voltage is configurable.
-
Patent Agency Ranking
公开(公告)号：US20250110526A1
公开(公告)日：2025-04-03
申请号：US18979763
申请日：2024-12-13
Inventor： Wei Chih Chen
Abstract: Systems and methods are provided for a clock generator is configured to generate N clock signals evenly spaced by phase. A clock generator includes a poly phase filter configured to utilize a differential clock signal to generate N intermediate signals, the intermediate signals being spaced approximately 360/N degrees apart in phase. A phase error corrector is configured to receive the intermediate signals and to generate N clock output signals, where a phase error is a measure of a difference in phase between consecutive ones of the clock output signals from 360/N degrees, the phase error corrector being configured to reduce phase error among the clock output signals based on a feedback signal. A phase error detection circuit is configured to receive the clock output signals and to generate the feedback signal based on detected phase errors among the clock output signals.
-
公开(公告)号：US20250105732A1
公开(公告)日：2025-03-27
申请号：US18372939
申请日：2023-09-26
Applicant: Keng Chen , Arvind Raghavan , Tamir Salus , Christopher Schaef , Huanhuan Zhang , Sivaraman Masilamani
Inventor： Keng Chen , Arvind Raghavan , Tamir Salus , Christopher Schaef , Huanhuan Zhang , Sivaraman Masilamani
Abstract: An apparatus includes a power converter with an input terminal and an output terminal. The apparatus further includes a first comparator. A first input of the first comparator is coupled to the output terminal of the power converter. The apparatus further includes a reference clock generator. An output of the reference clock generator is coupled to a second input of the first comparator. An input of the reference clock generator is coupled to a frequency comparator.
-
公开(公告)号：US12261581B2
公开(公告)日：2025-03-25
申请号：US17864188
申请日：2022-07-13
Applicant: Apple Inc.
Inventor： Alfred Erik Raidl , Antonio Passamani , Chia-Yu Hsieh
Abstract: Systems and methods for generating a radio frequency (RF) signal by a digital-to-analog converter (DAC) with transmission frequency within a wide transmission frequency range are described. An output reactance of the DAC coupled (directly or indirectly) to one or more antennas corresponds to the transmission frequency of the RF signals. Multiple embodiments of the DAC are described to include circuitry for tuning the output reactance of the DAC, and therefore, shifting a center frequency to select a transmission frequency range (from multiple transmission frequency ranges) for providing the RF signals.
-
公开(公告)号：US20250079996A1
公开(公告)日：2025-03-06
申请号：US18798458
申请日：2024-08-08
Inventor： Dominik Reinhard Beinlich
Abstract: The invention relates to an N-bit digital-to-analogue converter with an output voltage range and configured to provide as output an output voltage based on digital data received as input. The N-bit digital-to-analogue converter comprises at least one register, comprising an output data register having at least N bits and M enhancement bits, wherein the N-bit digital-to-analogue converter is configured to store the received digital data in the output data register and in the M enhancement bits; an evaluation logic configured to provide at least one binary evaluation signal derived from the received digital data; and a converter configured to receive the at least one binary evaluation signal, with the converter having access to the output data register and being configured to provide the output voltage based on the output data register and the received at least one binary evaluation signal.
-
公开(公告)号：US12224767B2
公开(公告)日：2025-02-11
申请号：US18167380
申请日：2023-02-10
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Artem Vitalyevich Cherenkov , Man Zhao , Mikhail Alexandrovich Linnik , Yijie Wang
Abstract: A signal processing apparatus includes a plurality of time-interleaving digital-to-analog converters each configured to sample a digital input signal at a preset sub-DAC sample frequency, and to generate an analog sub-DAC output signal. The signal processing apparatus includes analog multiplexer that samples the plurality of sub-DAC output signals at a preset multiplexer clock frequency and generates a multiplexer output signal. The signal processing apparatus further includes a local ADC that receives the multiplexer output signal and generate a digital feedback signal. The signal processing apparatus further includes a digital compensation engine that receives the digital feedback signal from the local ADC and determine one or more distortion compensation parameters. The signal processing apparatus further includes a digital pre-processing stage that receives the one or more distortion compensation parameters from the digital compensation engine and performs distortion compensation pre-processing on the digital input signal.
-
-
-
-
-
-
-
-
-
Search Results
4064
records
(took 0.028 seconds)
