POWER AMPLIFIER INTEGRATED CIRCUIT WITH TUNABLE IMPEDANCE MATCHING

    公开(公告)号:US20250167738A1

    公开(公告)日:2025-05-22

    申请号:US18590512

    申请日:2024-02-28

    Applicant: NXP B.V.

    Abstract: A power amplifier integrated circuit with a tunable impedance matching network and associated methods of testing and operation are provided. The power amplifier integrated circuit includes a power amplifier having an output, an output node coupled to the output of the power amplifier, and a tunable impedance matching network. The tunable impedance matching network includes a tunable inductor coupled to the output node. The tunable inductor includes switches configured to selectively modify an inductance of the tunable inductor. The switches may be configured to modify the tunable inductor to have different inductances in respective testing and functional modes.

    SYSTEM OF NETWORK SWITCHES
    2.
    发明申请

    公开(公告)号:US20250158938A1

    公开(公告)日:2025-05-15

    申请号:US18823261

    申请日:2024-09-03

    Applicant: NXP B.V.

    Abstract: A system comprising: a first and second network switch each comprising a plurality of ports for coupling to one or more devices; wherein the first and second network switches are communicably coupled; wherein the first network switch, based on receipt of a network frame at its ports, is configured to: process the network frame based on its content and a first rule set to determine network frame forwarding information for the network frame; add metadata to the network frame based on the result of said processing; forward the network frame with the added metadata to the second network switch; wherein the second network switch, based on receipt of the network frame, is configured to: read the metadata and process the network frame based on the network frame forwarding information as determined by the first network switch.

    WIPE-OUT AND VERIFICATION OF A NON-VOLATILE MEMORY

    公开(公告)号:US20250149099A1

    公开(公告)日:2025-05-08

    申请号:US18500150

    申请日:2023-11-02

    Applicant: NXP B.V.

    Abstract: A method is described for performing a wipe-out and verification of a plurality of non-volatile memory (NVM) cells. The method includes performing an operation to set all the plurality of NVM cells to a single state. The single state may be one of a conducing or non-conducting state depending on the NVM architecture. After the operation to set the cells to the single state is complete, the verification is performed. In the verification operation, all cells of the plurality of NVM cells are set to the single state by performing a single read operation on the plurality of NVM cells. Detection of one of a conducting or non-conducting path through the plurality of NVM cells is used to verify if all cells of the NVM array had their contents wiped out. A notification is provided in response to all cells not being set to the single known state.

    SYSTEM AND METHOD FOR DYNAMIC MANAGEMENT OF ULTRA-WIDEBAND RANGING SESSIONS

    公开(公告)号:US20250142332A1

    公开(公告)日:2025-05-01

    申请号:US18408998

    申请日:2024-01-10

    Applicant: NXP B.V.

    Abstract: An ultra-wideband (UWB) system of a UWB-enabled device dynamically schedules UWB ranging sessions with multiple asynchronous access control devices. The UWB system creates one ranging session for each access control device and schedules each ranging session with equal priority. During each ranging session, the UWB system receives a ranging message from a corresponding access control device, with the ranging message including a ranging management list (RML) that includes identifiers associated with UWB systems that are within an access control range of the corresponding access control device. The UWB system updates the priority of each ranging session based on presence or absence of the corresponding identifier in the RML of the received ranging message. Further, the UWB system schedules the ranging sessions with the updated priority to dynamically prioritize one access control device, thereby enabling an operation between the UWB system and the corresponding access control device.

    ACTIVE-DISCHARGE CONTROL IN FAIL SAFE STATE

    公开(公告)号:US20250141342A1

    公开(公告)日:2025-05-01

    申请号:US18926841

    申请日:2024-10-25

    Applicant: NXP B.V.

    Abstract: An inverter circuit, including: a first phase circuit including: a first transistor; a first gate driver configured to control the first transistor; a second transistor connected in series with the first transistor; and a second gate driver configured to control the second transistor; a microcontroller unit (MCU) configured to produce a first control signal and a second control signal to control an operation of the first gate driver and the second gate driver, respectively; and a power management circuit configured to: detect a failure in an operation of the MCU; and produce a third control signal and a fourth control signal to control the operation of the first gate driver and the second gate driver to control the discharge of the charging capacitor when the failure in the operation of the MCU is detected.

    MIMO radar system
    8.
    发明授权

    公开(公告)号:US12287423B2

    公开(公告)日:2025-04-29

    申请号:US17633271

    申请日:2020-07-24

    Applicant: NXP B.V.

    Abstract: The present disclosure relates to a MIMO radar system, comprising a first beamforming network (6) comprising a first beam ports (7A) and antenna ports (7B), wherein the first beamforming network is configured to connect the first beam ports via the first antenna ports to the first antenna elements, wherein the first beamforming network is configured to generate for each first beam port a single beam pattern. The first antenna elements transmitting or receiving a single beam pattern selected from the number of single beam patterns, wherein the first antenna elements are spaced apart at a first distance selected to provide a beam pattern of the first antenna array essentially consisting of a plurality of single main lobes. The radar system also has a similar second beamforming network (8). The second antenna elements of which are spaced apart at a second distance, larger than the first distance, the second distance being selected to provide a beam pattern of the second antenna array essentially consisting of multiple main lobes and multiple side lobes.

    Method and apparatus for determination of direction of arrival angle

    公开(公告)号:US12287391B2

    公开(公告)日:2025-04-29

    申请号:US17818016

    申请日:2022-08-08

    Applicant: NXP B.V.

    Abstract: An apparatus configured to receive an input dataset, x, indicative of radar signals reflected from targets as received at a plurality of antenna elements; define a matrix, A, formed of direction-of-arrival-angle vectors, an, each direction-of-arrival-angle vector representing an expected response at the plurality of antenna elements of radar signals from one of the targets; define a signal amplitude vector s to represent expected complex amplitudes as received in the radar signals; define an objective function based on x, A and s; search for a set of direction of arrival angles for each of the plurality of targets by the repeated evaluation of the objective function for a plurality of candidate matrices based on matrix A; and wherein said search space comprises a plurality of discrete points, z, associated with the direction of arrival angles by a function of sin(θk).

    MEMORY AND METHOD OF ACCESSING THE MEMORY

    公开(公告)号:US20250124976A1

    公开(公告)日:2025-04-17

    申请号:US18893493

    申请日:2024-09-23

    Applicant: NXP B.V.

    Abstract: A memory includes at least one memory bank which includes a set of memory arrays. Each memory cell includes a plurality of memory cells. The at least one memory bank includes: multiple word lines each connected to a corresponding row of the memory cells; a first decoder configured to receive address data, and decode the address data to provide intermediate data; a second decoder located in a central area of the memory bank between ones of the set of memory arrays, and configured to receive the intermediate data from the first decoder, and decode the intermediate data to provide selection data to the word lines. Memory cells addressable by a respective word line designated by the selection data are configured to be addressable by means of that selection data.

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