公开(公告)号：US20240022065A1

公开(公告)日：2024-01-18

申请号：US18350003

申请日：2023-07-11

Applicant: NXP B.V.

Inventor： Erik Santiago ,  Antoine Fabien Dubois ,  Pierre Philippe Calmes

IPC: H02H7/20 ,  H02H1/00

CPC classification number: H02H7/20 ,  H02H1/0007

Abstract: One example discloses a power controller configured to modulate a load current sent to a load, including: a first chip including a set of higher-power circuits configured to directly modulate the load current sent to the load; a second chip electrically coupled to the first chip and including a set of lower-power circuits; wherein the set of higher-power circuits are electrically isolated from the set of lower-power circuits; a power control path distributed between the first chip and the second chip, and configured to modulate the load current sent to the load; a diagnostics path distributed between the first chip and the second chip, and configured to monitor the higher-power circuits in the first chip and the lower-power circuits in the second chip for a set of fault conditions; wherein a portion of the diagnostics path in the second chip includes a plausibility circuit configured to compare a load current commanded by a first portion of the power control path in the second chip to the load current sent to the load by a second portion of the power control path in the first chip; and wherein the plausibility circuit is configured to transmit a safe-state request if the load current sent to the load is not equivalent to the load current commanded; and wherein the safe-state request is transmitted in parallel to the load current commanded by the first portion of the power control path in the second chip.

公开(公告)号：US20250141342A1

公开(公告)日：2025-05-01

申请号：US18926841

申请日：2024-10-25

Applicant: NXP B.V.

Inventor： Erik Santiago ,  Pierre Philippe Calmes ,  Maxime Clairet ,  Olivier Culie ,  Xavier Bourlot ,  Antoine Fabien Dubois

IPC: H02M1/32 ,  H02M7/537 ,  H02P27/06 ,  H03K17/687

Abstract: An inverter circuit, including: a first phase circuit including: a first transistor; a first gate driver configured to control the first transistor; a second transistor connected in series with the first transistor; and a second gate driver configured to control the second transistor; a microcontroller unit (MCU) configured to produce a first control signal and a second control signal to control an operation of the first gate driver and the second gate driver, respectively; and a power management circuit configured to: detect a failure in an operation of the MCU; and produce a third control signal and a fourth control signal to control the operation of the first gate driver and the second gate driver to control the discharge of the charging capacitor when the failure in the operation of the MCU is detected.