-
公开(公告)号：US12199624B2
公开(公告)日：2025-01-14
申请号：US18311073
申请日：2023-05-02
Applicant: Honeywell International Inc.
Inventor： Chad Fertig , Karl D. Nelson
Abstract: An atomic clock is provided. An output of a tunable LO is coupled to a user output of the atomic clock. A charge pump adjusts the tunable LO with a LO tuning voltage. A follower circuit sets an output frequency of the atomic clock to a frequency of an external reference signal coupled to an external reference input. An atom referenced circuit sets the output frequency of the atomic clock to a frequency based on stored operating settings. A controller stores then current operating settings generated based on a then current external reference signal coupled to the external reference input. The controller is further configured to apply the stored then current operating settings to the atom referenced circuit when the then current external reference signal is removed from the external reference input to maintain the output frequency of the atomic clock at the output frequency set by the follower circuit.
-
2.发明申请公开(公告)号：US20240429922A1
公开(公告)日：2024-12-26
申请号：US18432059
申请日：2024-02-05
Applicant: HTC Corporation
Inventor： Sheng-Long Wu , Wei-Chih Kuo , Shih-Yao Tsai , Li-Wei Lin , Chao Shuan Huang
Abstract: A synchronization signal generation circuit and a synchronization method among a plurality of devices are proposed. The synchronization signal generation circuit includes a clock signal generator and a controller. The clock signal generator generates a reference clock signal. The controller receives an input clock signal from a host end device and generates a plurality of candidate clock signals through a plurality of counting operations based on the reference clock signal. The controller selectively transmits one of the candidate clock signals to each peripheral device according to request information corresponding to each peripheral device. The candidate clock signals and the input clock signal have mutually aligned start time points in each frame period.
-
公开(公告)号：US20230412162A1
公开(公告)日：2023-12-21
申请号：US18356218
申请日：2023-07-21
Inventor： MAO-RUEI LI , MING HSIEN TSAI , RUEY-BIN SHEEN
IPC: H03K7/08 , G06F30/20 , G04F10/00 , H03K3/017 , H03K5/156 , H03L7/085 , H03L7/06 , G11C16/32 , G06F30/337 , G04F10/04
CPC classification number: H03K7/08 , G06F30/20 , G04F10/005 , H03K3/017 , H03K5/1565 , H03L7/085 , H03L7/06 , G11C16/32 , G06F30/337 , G04F10/04
Abstract: A circuit includes a period calculator and a pulse width calculator. The period calculator is configured for receiving a first predetermined digital code and a second predetermined digital code, and for calculating a first calculated period value according to the first predetermined digital code, and calculating a second calculated period value according to the second predetermined digital code. The first predetermined digital code has a first predetermined period value, and the second predetermined digital code has a second predetermined period value. The pulse width calculator is configured for receiving a predetermined pulse width, and calculating a first pulse width code corresponding to the predetermined pulse width according to the first predetermined period value, the second predetermined period value, the first calculated period value, the second calculated period value and the predetermined pulse width.
-
公开(公告)号：US20230336325A1
公开(公告)日：2023-10-19
申请号：US17720087
申请日：2022-04-13
Applicant: STMicroelectronics S.r.l.
Inventor： Francesco Pappalardo , Elena Salurso
CPC classification number: H04L7/0331 , H03L7/06
Abstract: A method of processing a data stream includes taking a first number of samples of the data stream using a sampling clock over a first observation window and storing a stored data stream including the first number of samples in a data buffer. A length of the first observation window is determined by a reference clock. A measured number of cycles of the sampling clock are determined from the first number of samples. An error between an expected number of cycles of the sampling clock and the measured number of cycles of the sampling clock in the observation window is measured. The stored data stream corresponding to the first observation window is updated to contain a second number of samples by correcting the first number of samples with the error.
-
公开(公告)号：US20230006677A1
公开(公告)日：2023-01-05
申请号：US17942077
申请日：2022-09-09
Applicant: Marc Loinaz
Inventor： Marc Loinaz
Abstract: A sensor network, which includes a sensor controller serially coupled to a plurality of sensor modules, is configured to program the sensor modules so as to transfer measurement data to the sensor controller and to synchronize the sensor modules to picosecond accuracy via on-chip or on-module custom circuits and a physical layer protocol. The sensor network has applications for use in PET, LiDAR or FLIM applications. Synchronization, within picosecond accuracy, is achieved through use of a picosecond time digitization circuit. Specifically, the picosecond time digitization circuit is used to measure on-chip delays with high accuracy and precision. The delay measurements are directly comparable between separate chips even with voltage and temperature variations between chips.
-
Patent Agency Ranking
公开(公告)号：US11249509B2
公开(公告)日：2022-02-15
申请号：US16993231
申请日：2020-08-13
Applicant: AMBIQ MICRO, INC.
Inventor： Scott Hanson
IPC: H03L7/18 , G06F1/06 , H03L7/06 , H03L7/181 , G06F1/3237 , G06F1/3287 , G06F1/12 , G06F11/30 , G06F11/34 , G06F13/10 , G01R19/00 , G05F1/56 , H03K17/687 , H03M1/12 , H03L7/00 , G05F1/575 , G06F1/3296 , H02M3/158 , H02M1/00
Abstract: An adaptive voltage converter adapted to compensate for the exponential sensitivities of sub-threshold and near-threshold circuits. The converter can change its power/performance characteristics between different energy modes. The converter may comprise two or more voltage converters/regulators. A multiplexing circuit selects between the outputs of the several converters/regulators depending on the state of a control signal generated by a control facility. The converter is specially adapted to change the output of each converter/regulator based on a number of variables, including, for example, process corner, temperature and input voltage.
-
公开(公告)号：US20220038103A1
公开(公告)日：2022-02-03
申请号：US17391544
申请日：2021-08-02
Applicant: CommScope Technologies LLC
Inventor： Stuart D. Sandberg
Abstract: In one embodiment, a local clock is synchronized to a master clock using a Kalman filter to determine state variables using a state transition matrix that includes at least one coefficient that is associated with a digital-to-analog converter (DAC), where the state variables include a unit step variable indicative of a unit step for the system. The local clock is controlled based on the state variables determined using the Kalman filter. The unit step is indicative of an amount by which the frequency of the local clock signal changes in response to a change in the digital input of the DAC.
-
8.发明授权公开(公告)号：US11218155B2
公开(公告)日：2022-01-04
申请号：US17101665
申请日：2020-11-23
Applicant: Ciena Corporation
Inventor： Tingjun Wen , Sadok Aouini , Naim Ben-Hamida , Mahdi Parvizi , Matthew Mikkelsen
Abstract: Described is a digital fractional phase locked loop (DFPLL) with a current mode low pass filter. The DFPLL includes a binary phase frequency detector (BPFD) configured to output a directional pulse based on comparison of a reference clock and a feedback clock, a current mode low pass filter connected to the BPFD, and a current controlled oscillator (CCO) connected to the current mode low pass filter. The current mode low pass filter configured to output a control current based on at least the directional pulse when a current steering switch directly controlled by the directional pulse switches to the CCO. The CCO configured to adjust a frequency of the CCO based on the control current to generate an output clock. The feedback clock based on the output clock and the reference clock aligned with the feedback clock by adjusting the frequency of the output clock until frequency and phase lock.
-
公开(公告)号：US11212071B2
公开(公告)日：2021-12-28
申请号：US16595654
申请日：2019-10-08
Applicant: DENSO CORPORATION
Inventor： Nobuaki Matsudaira
IPC: H04L7/033 , H04L29/06 , H03L7/00 , H04B1/10 , H04B3/06 , H04L7/00 , H04L12/40 , H04L25/03 , H04L7/10 , H03L7/06
Abstract: A receiver includes: an A/D converter that performs an analog digital conversion of an input signal; an equalizer that equalizes an output from the A/D converter, eliminates inter code interference and obtains a data output; a timing recovery part that generates a recovery clock from the data output of the equalizer; a detector that detects the timing when an input signal varies from a no-signal state and has reached a predetermined threshold; and an initial phase setting part that sets as the initial phase of the recovery clock by the timing recovery part, a timing when the predetermined time has elapsed after the timing detected by the detector.
-
公开(公告)号：US11206051B2
公开(公告)日：2021-12-21
申请号：US16896557
申请日：2020-06-09
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Debapriya Sahu , Srinivas Venkata Veeramreddi , Raghu Ganesan
Abstract: A device includes a frequency multiplier circuit to receive a base frequency signal, multiply the base frequency signal, and output the multiple of the base frequency signal, and includes an offset frequency generator, including at least one logic gate, to receive the multiple of the base frequency signal and output an offset frequency signal from the at least one logic gate combination. A mixing circuit receives the offset frequency signal and a digital data signal, converts the digital data signal into an analog representation of the digital data signal, and mixes the offset frequency signal and the analog representation of the digital data signal to produce a mixed signal. The device yet further includes a power amplifier to amplify the mixed signal and output the amplified mixed signal as an output frequency signal of the device.
-
-
-
-
-
-
-
-
-
Search Results
5576
records
(took 0.02 seconds)
