公开(公告)号：US20250071709A1

公开(公告)日：2025-02-27

申请号：US18882196

申请日：2024-09-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongjin KANG ,  Duhe JANG ,  Byungseok SOH ,  Hyungyong LEE ,  Chanho JUNG

IPC: H04W56/00 ,  G06F1/12

Abstract: An electronic device includes a communication circuit including a first interface and a second interface, a memory storing instructions, and a processor communicatively coupled with the communication circuit via the first interface or via the second interface. The processor is configured to execute the instructions to send, to the communication circuit via the first interface, a request for clock information of the communication circuit, receive, from the communication circuit via the first interface, the clock information of the communication circuit, receive, from the communication circuit via the second interface, an interrupt signal and first time information corresponding to the interrupt signal being generated, and generate clock information of the processor based on the clock information of the communication circuit and the first time information.

公开(公告)号：US12235674B2

公开(公告)日：2025-02-25

申请号：US18223281

申请日：2023-07-18

Applicant: B&R INDUSTRIAL AUTOMATION GMBH

Inventor： Oliver Hoeftberger ,  Franz Profelt

IPC: G06F1/12 ,  G06F1/14

Abstract: Method for time synchronization in a network between at least one master and at least one slave, which is an interrupt-capable network component and uses a timer, which accesses a slave time to generate at least one interrupt recurring at a predefined cycle duration, at a respective trigger point in time that is synchronized with the slave time. When a synchronization message arrives, a time offset between the master time and the slave time is determined in the slave, and a time fraction is determined from the time offset, which corresponds to an integer multiple of the predefined cycle duration of the at least one interrupt. An interrupt offset is then determined from the time fraction and the time offset. At least one time jump is carried out by a synchronization unit in the slave to correct the time offset.

公开(公告)号：US12228961B2

公开(公告)日：2025-02-18

申请号：US18629138

申请日：2024-04-08

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G06F1/12 ,  G06F1/04 ,  G06F1/08 ,  G11C7/02 ,  G11C7/04 ,  G11C7/10 ,  G11C7/22 ,  G06F1/06 ,  G06F1/10

Abstract: The disclosed embodiments relate to a memory system that generates a multiplied timing signal from a reference timing signal. During operation, the system receives a reference timing signal. Next, the system produces a multiplied timing signal from the reference timing signal by generating a burst comprising multiple timing events for each timing event in the reference timing signal, wherein consecutive timing events in each burst of timing events are separated by a bit time. Then, as the reference clock frequency changes, the interval between bursts of timing events changes while the bit time remains substantially constant.

公开(公告)号：US20250054561A1

公开(公告)日：2025-02-13

申请号：US18809250

申请日：2024-08-19

Applicant: Rambus Inc.

Inventor： Yohan U. Frans ,  Wayne F. Ellis ,  Akash Bansal

IPC: G11C29/50 ,  G01R23/02 ,  G01R23/15 ,  G01R35/00 ,  G06F1/08 ,  G06F1/12 ,  G06F11/16 ,  G06F13/16 ,  G11C7/04 ,  G11C7/22 ,  G11C8/18 ,  G11C29/02 ,  H03L1/02

Abstract: The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit.

公开(公告)号：US20250044828A1

公开(公告)日：2025-02-06

申请号：US18922797

申请日：2024-10-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongun Jeong ,  Donghyeok Jeong ,  ChangSik Yoo ,  Kihan Kim

IPC: G06F1/12

Abstract: Disclosed is a clock multiplexing circuit which includes a first transistor that is between a first input terminal that receives a first input clock signal and an output terminal that outputs an output pulse signal and operates based on a logic level of a second input terminal receiving a second input clock signal, and a second transistor that is between the output terminal and a first voltage node and operates based on the logic level of the second input terminal. The first input clock signal and the second input clock signal have the same period and have different phases. The output pulse signal transitions to a first logic level at a first time when the first input clock signal transitions to the first logic level and transitions to a second logic level at a second time when the second input clock signal transitions to the first logic level.

公开(公告)号：US12210934B2

公开(公告)日：2025-01-28

申请号：US17583083

申请日：2022-01-24

Applicant: Tencent Technology (Shenzhen) Company Limited

Inventor： Hualiang Zhang ,  Guanglei Xi ,  Mengyu Zhang ,  Fuming Liu ,  Qiaonian Yu ,  Yicong Zheng ,  Shengyu Zhang

IPC: G06F1/12 ,  G06F13/42 ,  G06N10/40 ,  G06N10/70 ,  G06N10/80 ,  H04L5/00 ,  H04L7/00

Abstract: This application discloses a clock synchronization system, including a quantum control processor (QCP) and N digital/analog mutual conversion devices, each digital/analog mutual conversion device including a frequency conversion module and a signal synchronization module that includes a D flip-flop (DFF). The QCP generates a global synchronization signal and reference clock signals; and transmits the global synchronization signal and a reference clock signal to the frequency conversion module and transmits the global synchronization signal to the signal synchronization module of each conversion device. The frequency conversion module performs frequency conversion processing on the reference clock signal to obtain a target clock signal, and generates a signal synchronization instruction according to the global synchronization signal; and transmits the signal synchronization instruction and the target clock signal to the signal synchronization module. The signal synchronization module performs, based on the global synchronization signal, signal synchronization on the target clock signal through the DFF.

公开(公告)号：US12210373B2

公开(公告)日：2025-01-28

申请号：US18165855

申请日：2023-02-07

Applicant: STMicroelectronics International N.V.

Inventor： Ankur Bal ,  Sharad Gupta ,  Anupam Jain

IPC: G06F1/12 ,  G06F1/08 ,  G06F1/10

Abstract: An integrated circuit includes a first subsystem including a first clock generator configured to generate a first clock signal. The integrated circuit also includes a second subsystem including a second clock generator configured to generate a second clock signal. The first subsystem includes an edge detector configured to detect an edge of the second clock signal. The first clock generator generates the first clock signal with a selected phase relative to the second clock signal based on the edge of the second clock signal.

公开(公告)号：US20250028592A1

公开(公告)日：2025-01-23

申请号：US18354177

申请日：2023-07-18

Applicant: Western Digital Technologies, Inc.

Inventor： Shuli SHMAYA ,  Eran MOSHE

IPC: G06F11/07 ,  G06F1/12

Abstract: Instead of allowing an electrostatic discharge (ESD) event to cause a lost clock signal sync due effects of the ESD event causing an SSD to enter low power mode, utilizing ESD detection can be used to stop the reference clock signal to avoid involuntary low power mode. When an ESD event occurs, an ESD antenna sensor will selectivity disable sensitive signals and the reference clock signal. Once the ESD detector recognizes an ESD event has occurred, the device is able to enter freeze mode. While the reference clock signal is in freeze mode, the input signals are bypassed to avoid lost clock signal sync. Once the ESD event is done, the controller notifies the host to restart the reference clock signal and resume clock signal sync.

公开(公告)号：US12205673B1

公开(公告)日：2025-01-21

申请号：US17945902

申请日：2022-09-15

Applicant: Cadence Design Systems, Inc.

Inventor： Hari Anand Ravi ,  Sachin Ramesh Gugwad ,  Jitendra Kumar Yadav ,  Thomas Evan Wilson ,  Vinod Kumar

IPC: G11C8/18 ,  G06F1/12 ,  G06F13/20 ,  G11C7/22

Abstract: Various embodiments described herein provide for a read data strobe (RDQS) path having variation compensation (e.g., voltage and temperature compensation), delay lines, or both, where the RDQS path can be included by a physical (PHY) interface for a memory device, such as a Double Data Rate (DDR) Dynamic Random-Access Memory (DRAM) memory device.

公开(公告)号：US20250021130A1

公开(公告)日：2025-01-16

申请号：US18349976

申请日：2023-07-11

Applicant: Mellanox Technologies, Ltd.

Inventor： Natan Manevich ,  Dotan David Levi ,  Wojciech Wasko ,  Maciej Machnikowski

IPC: G06F1/12

Abstract: In one embodiment, a system including a reference processing device includes a reference hardware clock to maintain a reference clock value, and reference clock synchronization circuitry to discipline the reference hardware clock responsively to a remote clock, which is remote to the system, and a follower processing device including a follower hardware clock to maintain a follower clock value, and follower clock synchronization circuitry to synchronize the follower hardware clock to the reference hardware clock, and provide an indication about the follower clock value to the reference processing device, wherein the reference clock synchronization circuitry is configured to monitor a quality of the synchronization of the follower hardware clock to the reference hardware clock.