公开(公告)号：US12228670B2

公开(公告)日：2025-02-18

申请号：US16447985

申请日：2019-06-21

Applicant: NXP USA, Inc.

Inventor： Olivier Doaré ,  Didier Salle ,  Cristian Pavao Moreira ,  Julien Orlando ,  Jean-Stephane Vigier ,  Andres Barrilado Gonzalez

IPC: G01S7/00 ,  G01S7/35 ,  G06F1/10 ,  G06F1/12 ,  H03L7/08 ,  H03M1/12

Abstract: A communication unit includes a plurality of cascaded devices that include at least one master device and at least one slave device configured in a master-slave arrangement. The at least one master device and at least one slave device each include: a demodulator circuit configured to receive a distributed reference clock signal and re-create a system clock signal therefrom; a clock generation circuit that includes an internally-generated reference phase locked loop configured to receive the re-created system clock signal to create a master-slave clock signal; and an analog-to-digital converter, ADC, coupled to the reference phase locked loop and configured to use a same master-slave clock signal to align respective sampling instants between each ADC of the at least one master device and at least one slave device.

公开(公告)号：US12222749B2

公开(公告)日：2025-02-11

申请号：US18154173

申请日：2023-01-13

Applicant: ELECTRICITY EXCHANGE DAC

Inventor： Paddy Finn

IPC: G06F1/12 ,  G06F1/10 ,  G06F1/26 ,  G06F11/22 ,  G06F13/36 ,  G08B13/14 ,  H04L7/00 ,  H02J13/00

Abstract: A modular system is described which can provide high frequency monitoring of power use and responsive control as well as enabling network connectivity for centralised monitoring and operation. One modular system consists of a communications bus, end caps, and a combination of the modules providing communications, power metering, relay control and battery backup. Each modular system can be configured with a combination of modular units as needed for the application. A combination of bus communication monitoring and tilt detection provides security against external tampering after installation.

公开(公告)号：US20250044826A1

公开(公告)日：2025-02-06

申请号：US18763965

申请日：2024-07-03

Applicant: Micron Technology, Inc.

Inventor： Marcos Alvarez Gonzalez ,  Andrea Sorrentino ,  Morshed Mohammed ,  Luiza Souza Correa ,  Wolfgang Anton Spirkl ,  Paritosh Piyush Sahu ,  Martin Bach ,  Ronny Schneider

IPC: G06F1/10

Abstract: Methods, systems, and devices for techniques for coupled host and memory dies are described. As part of a low-speed testing phase of a memory system, a low-speed tester may measure the change in phase of a set of clock signals in response to a change in a configuration of the memory system. For example, the low-speed tester may communicate with a mimic circuit of the memory system to determine a first frequency of a first clock signal of the multi-phase clock associated with a first configuration of the memory system and determine a second frequency of the first clock signal associated with a second configuration of the memory system. The low-speed tester may store an indication of the difference between the first frequency and the second frequency, and a high-speed tester may use the difference as part of selecting a set of trim parameters for the multi-phase clock signal.

公开(公告)号：US20250036582A1

公开(公告)日：2025-01-30

申请号：US18917555

申请日：2024-10-16

Applicant: d-MATRIX CORPORATION

Inventor： Sudeep BHOJA ,  Siddharth SHETH

IPC: G06F13/16 ,  G06F1/10 ,  G06F13/42

Abstract: An AI accelerator apparatus using in-memory compute chiplet devices. The apparatus includes one or more chiplets, each of which includes a plurality of tiles. Each tile includes a plurality of slices, a central processing unit (CPU), and a hardware dispatch device. Each slice can include a digital in-memory compute (DIMC) device configured to perform high throughput computations. In particular, the DIMC device can be configured to accelerate the computations of attention functions for transformer-based models (a.k.a. transformers) applied to machine learning applications. A single input multiple data (SIMD) device configured to further process the DIMC output and compute softmax functions for the attention functions. The chiplet can also include die-to-die (D2D) interconnects, a peripheral component interconnect express (PCIe) bus, a dynamic random access memory (DRAM) interface, and a global CPU interface to facilitate communication between the chiplets, memory and a server or host system.

公开(公告)号：US12212328B2

公开(公告)日：2025-01-28

申请号：US18326348

申请日：2023-05-31

Applicant: Analog Devices, Inc.

Inventor： Reuben P. Nelson

IPC: H03L7/08 ,  G06F1/10 ,  G06F1/12 ,  H03L7/107 ,  H03K5/00 ,  H04B1/16

Abstract: Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation.

公开(公告)号：US12197266B2

公开(公告)日：2025-01-14

申请号：US17992406

申请日：2022-11-22

Applicant: GoPro, Inc.

Inventor： Alexis Lefebvre ,  Vincent Vacquerie

IPC: G06F1/00 ,  G06F1/10 ,  G06F1/3225 ,  G06F1/3296 ,  G06F1/3203

Abstract: Systems and methods are disclosed for dynamic power allocation for memory using multiple interleaving patterns. For example, a system may include a set of memory devices, including a first subset and a second subset, and a memory management circuitry configured to translate virtual addresses into physical addresses of memory locations in the set of memory devices using a first interleaving pattern when operating in a first mode; and translate virtual addresses using a second interleaving pattern when operating in a second mode. The first and second interleaving patterns both map virtual addresses in a first range exclusively to memory devices in the first subset. The first interleaving pattern maps virtual addresses in a second range to memory devices in the first subset and in the second subset. The second interleaving pattern maps virtual addresses in the second range exclusively to memory devices in the first subset.

公开(公告)号：US12197242B2

公开(公告)日：2025-01-14

申请号：US18184009

申请日：2023-03-15

Applicant: SigmaSense, LLC.

Inventor： Richard Stuart Seger, Jr. ,  Daniel Keith Van Ostrand ,  Patrick Troy Gray ,  Michael Shawn Gray ,  Timothy W. Markison

IPC: G06F1/10 ,  H03K19/17784 ,  H03M1/12 ,  H04B1/00

Abstract: A programmable drive-sense unit (DSU) includes a drive-sense circuit operably coupled to a load, wherein the drive-sense circuit is configured to drive and simultaneously to sense the load via a single line, and produce an analog output based on the sensing the load. The programmable DSU also includes an analog to digital circuit operably coupled to the drive-sense circuit, where the analog to digital circuit is operable to generate a digital output based on the analog output and in accordance with one or more programmable operational parameters to achieve one or more of load sensing objectives associated with the sensing of the load and data processing objectives associated with the sensing of the load.

公开(公告)号：US12189416B2

公开(公告)日：2025-01-07

申请号：US18094227

申请日：2023-01-06

Applicant: SK hynix Inc.

Inventor： Yeon Ho Lee ,  Yong Suk Choi

IPC: G06F1/08 ,  G06F1/10 ,  G06F1/12

Abstract: A clock generating circuit includes a buffer circuit and a phase compensating circuit. The buffer circuit buffers an input clock signal to generate an output clock signal. The phase compensating circuit detects a noise in a power voltage and adjusts, according to the noise of the power voltage, a voltage level of the input clock signal to compensate for a phase change of the output clock signal due to the noise of the power voltage.

公开(公告)号：US20240403174A1

公开(公告)日：2024-12-05

申请号：US18803179

申请日：2024-08-13

Applicant: Oracle International Corporation

Inventor： Virendra Marathe ,  Alex Kogan ,  Ahmed Alquraan

IPC: G06F11/14 ,  G06F1/10 ,  G06F1/14 ,  G06F11/20 ,  G06F16/27

Abstract: Systems and methods are disclosed to improve disaster recovery by implementing a scalable low-loss disaster recovery for a data store. The disaster recovery system enables disaster recovery for a linearizable (e.g., externally consistent) distributed data store. The disaster recovery system also provides for a small lag on the backup site relative to the primary site, thereby reducing the data loss by providing a smaller data loss window compared to traditional disaster recovery techniques. The disaster recovery system implements a timestamp for log records based on a globally synchronized clock. The disaster recovery system also implements a watermark service that updates a global watermark timestamp that a backup node uses to apply log records.

公开(公告)号：US20240377855A1

公开(公告)日：2024-11-14

申请号：US18485562

申请日：2023-10-12

Applicant: NXP B.V.

Inventor： Siyaram Sahu ,  Anand Kumar Sinha ,  Krishna Thakur

IPC: G06F1/10 ,  G06F1/08

Abstract: A clock generator includes a buffer stage to drive an output clock and a slew accelerator circuit to receive a first clock signal and generate an input clock signal to the buffer stage. The slew accelerator circuit includes first, second, and third inverter stages. The first stage generates a pair of non-overlapping clock signals from the first clock signal. A rise time of a first non-overlapping clock signal of the pair is faster than a rise time of a second non-overlapping clock signal of the pair, and a fall time of the second non-overlapping clock signal is faster than a fall time of the first non-overlapping clock signal. The second stage generates a first intermediate clock signal based on the pair of non-overlapping clock signals. The third stage generates the input clock signal to the buffer stage based on the first intermediate clock signal and the pair of non-overlapping clocks.