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公开(公告)号：US20200057138A1
公开(公告)日：2020-02-20
申请号：US16410013
申请日：2019-05-13
申请人： NXP USA, INC.
摘要： A radar device (100) is described that includes at least one transceiver (105) configured to support frequency modulated continuous wave (FMCW); radar device (100) and a digital controller (262). A temperature sensor system includes a plurality of temperature sensors (222, 232, 242) coupled to one or more circuits (220, 230, 240) in the at least one transceiver (105). The digital controller (262, 306) comprises or is operably coupled to an over-temperature emulation circuit (308) configured to emulate an over-temperature shutdown state by injecting an over-temperature force signal (290) into the temperature sensor system (270).
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公开(公告)号：US11018844B2
公开(公告)日：2021-05-25
申请号：US16433520
申请日：2019-06-06
申请人： NXP USA, INC.
IPC分类号： H04L7/00 , G01S13/931 , G06F9/30
摘要： A method for synchronizing a cascaded RADAR system (80) includes modulating (320) with a master RADAR system (12), an amplitude of a sequence of clock cycles of a clock (70) in response to a Ramp Frame Start (RFS) signal (92). The master RADAR system determines (322) a duration (310, 312, 314) of the sequence of clock cycles based on a code. A slave RADAR system (14) demodulates (324) the sequence of clock cycles to recover the clock and the RFS signal, wherein a clock leading edge of the clock is phase aligned to an RFS leading edge of the RFS signal. The slave RADAR system decodes (326) the code from the duration of the sequence of clock cycles, wherein the code determines an action performed by the slave RADAR system in response to receiving a data signal from the master RADAR system.
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公开(公告)号：US11353550B2
公开(公告)日：2022-06-07
申请号：US16410013
申请日：2019-05-13
申请人： NXP USA, INC.
摘要： A radar device (100) is described that includes at least one transceiver (105) configured to support frequency modulated continuous wave (FMCW); radar device (100) and a digital controller (262). A temperature sensor system includes a plurality of temperature sensors (222, 232, 242) coupled to one or more circuits (220, 230, 240) in the at least one transceiver (105). The digital controller (262, 306) comprises or is operably coupled to an over-temperature emulation circuit (308) configured to emulate an over-temperature shutdown state by injecting an over-temperature force signal (290) into the temperature sensor system (270).
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公开(公告)号：US20200003883A1
公开(公告)日：2020-01-02
申请号：US16447962
申请日：2019-06-21
申请人： NXP USA, Inc.
发明人： Olivier Doaré , Didier Salle , Cristian Pavao Moreira , Julien Orlando , Jean-Stephane Vigier , Andres Barrilado Gonzalez
摘要： A communication unit (700) is described that includes a plurality of cascaded devices that comprise at least one master device (710) and at least one slave device (720, 723) configured in a master-slave arrangement. The at least one master device (710) and at least one slave device (720, 723) each comprise: an analog-to-digital converter, ADC, (741, 742) configured to use a same re-created system clock signal (788, 790) to align respective sampling instants between each ADC (741, 742). The at least one master device (710) comprises: a clock generation circuit comprising an internally-generated reference phase locked loop circuit (708), configured to output a system clock signal (782, 784); and a modulator circuit (762) coupled to the clock generation circuit and configured to receive and distribute the system clock signal (784). The at least one master device (710) and at least one slave device (720, 723) each comprise: a demodulator circuit (764, 765) configured to receive the distributed system clock signal (784) and re-create therefrom a synchronized system clock signal (788, 790) used by a respective ADC, (741, 742) of each of the the master device (710) and at least one slave device (720).
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公开(公告)号：US20190386810A1
公开(公告)日：2019-12-19
申请号：US16433520
申请日：2019-06-06
申请人： NXP USA, INC.
摘要： A method for synchronizing a cascaded RADAR system (80) includes modulating (320) with a master RADAR system (12), an amplitude of a sequence of clock cycles of a clock (70) in response to a Ramp Frame Start (RFS) signal (92). The master RADAR system determines (322) a duration (310, 312, 314) of the sequence of clock cycles based on a code. A slave RADAR system (14) demodulates (324) the sequence of clock cycles to recover the clock and the RFS signal, wherein a clock leading edge of the clock is phase aligned to an RFS leading edge of the RFS signal. The slave RADAR system decodes (326) the code from the duration of the sequence of clock cycles, wherein the code determines an action performed by the slave RADAR system in response to receiving a data signal from the master RADAR system.
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公开(公告)号：US11054513B2
公开(公告)日：2021-07-06
申请号：US16447962
申请日：2019-06-21
申请人： NXP USA, Inc.
发明人： Olivier Doaré , Didier Salle , Cristian Pavao Moreira , Julien Orlando , Jean-Stephane Vigier , Andres Barrilado Gonzalez
IPC分类号： G01S13/34 , G01S7/35 , G01S7/40 , G01S13/931
摘要： A communication unit (700) is described that includes a plurality of cascaded devices that comprise at least one master device (710) and at least one slave device (720, 723) configured in a master-slave arrangement. The at least one master device (710) and at least one slave device (720, 723) each comprise: an analog-to-digital converter, ADC, (741, 742) configured to use a same re-created system clock signal (788, 790) to align respective sampling instants between each ADC (741, 742). The at least one master device (710) comprises: a clock generation circuit comprising an internally-generated reference phase locked loop circuit (708), configured to output a system clock signal (782, 784); and a modulator circuit (762) coupled to the clock generation circuit and configured to receive and distribute the system clock signal (784). The at least one master device (710) and at least one slave device (720, 723) each comprise: a demodulator circuit (764, 765) configured to receive the distributed system clock signal (784) and re-create therefrom a synchronized system clock signal (788, 790) used by a respective ADC, (741, 742) of each of the the master device (710) and at least one slave device (720).
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公开(公告)号：US20200057140A1
公开(公告)日：2020-02-20
申请号：US15999181
申请日：2018-08-17
申请人： NXP USA, Inc.
摘要： A chirp linearity detector, integrated circuit, and method are provided. The chirp linearity detector comprises a phase-locked loop (PLL) frequency sampling circuit and a frequency sweep linearity measuring circuit. The PLL frequency sampling circuit comprises a frequency divider circuit for receiving a PLL output signal from a PLL and for providing a frequency divided output signal, a first low pass filter circuit for receiving the frequency divided output signal, for reducing harmonic mixing, and for providing a mixer input signal, a mixer circuit for receiving the mixer input signal, for mixing the mixer input signal with a local oscillator signal, and for providing a mixer output signal, a second low pass filter circuit for performing anti-aliasing filtering and for providing an analog-to-digital converter (ADC) input signal, and an ADC circuit for digitizing the ADC input signal and for providing a digital output signal.
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公开(公告)号：US20200003862A1
公开(公告)日：2020-01-02
申请号：US16447985
申请日：2019-06-21
申请人： NXP USA, Inc.
发明人： Olivier Doaré , Didier Salle , Cristian Pavao Moreira , Julien Orlando , Jean-Stephane Vigier , Andres Barrilado Gonzalez
摘要： A communication unit (900) includes a plurality of cascaded devices that comprise at least one master device (910) and at least one slave device (920, 923) configured in a master-slave arrangement. The at least one master device (910) and at least one slave device (920, 923) each include: a demodulator circuit (964, 965) configured to receive a distributed reference clock signal (984) and re-create a system clock signal (988, 990) therefrom; a clock generation circuit comprising an internally-generated reference phase locked loop configured to receive the re-created system clock signal (988, 990) to create a master-slave clock signal; and an analog-to-digital converter, ADC, (941, 942) coupled to the reference phase locked loop and configured to use a same master-slave clock signal (988, 990) to align respective sampling instants between each ADC (941, 942) of the at least one master device (910) and at least one slave device (920, 923).
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公开(公告)号：US20180121282A1
公开(公告)日：2018-05-03
申请号：US15705332
申请日：2017-09-15
申请人： NXP USA, Inc.
发明人： Andres Barrilado Gonzalez , Ralf Reuter , Dominique Delbecq , Francesco d'Esposito , Arnaud Sion , Gustavo Adolfo Guarin Aristizabal , Marcel Christoph Welpot
CPC分类号： G06F11/1004 , G06F3/0619 , G06F3/064 , G06F3/0683 , G06F11/08 , G06F11/10
摘要： A system for register error detection is described, the system comprising: a plurality of addressable registers comprising sets of registers, the registers in each set having contiguous addresses; a cyclic redundancy check generator coupled to the addressable registers and configured to determine a cyclic-redundancy-check result for each set of registers from the values of each of the respective set of registers; a controller coupled to the registers and the cyclic-redundancy-check generator. The controller comprises a cyclic-redundancy-check calculator and is configured to determine an expected cyclic-redundancy-check result from expected values for each of the set of registers, to read the cyclic-redundancy-check result for each of the set of registers determined by the cyclic-redundancy-check generator, and to compare the generated cyclic-redundancy-check result with the calculated cyclic-redundancy-check result and wherein a difference between the generated cyclic-redundancy-check result and the calculated cyclic-redundancy-check result is indicative of an error condition.
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