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    SYSTEM AND METHOD FOR TRACKING CONTENT TIMELINE IN THE PRESENCE OF PLAYBACK RATE CHANGES
    3.
    发明公开
    SYSTEM AND METHOD FOR TRACKING CONTENT TIMELINE IN THE PRESENCE OF PLAYBACK RATE CHANGES 审中-公开

    公开(公告)号：US20240007712A1

    公开(公告)日：2024-01-04

    申请号：US18344792

    申请日：2023-06-29

    Applicant: Verance Corporation

    Inventor： Patrick George Downes ,  Rade Petrovic

    IPC: H04N21/472 ,  G06F11/08 ,  H04N21/8358 ,  H04N21/4147

    CPC classification number: H04N21/47217 ,  G06F11/08 ,  H04N21/8358 ,  H04N21/4147

    Abstract: A system and method for controlling a media player for replacement content, such as dynamic ad insertion. The system tracks video watermarks from a content stream, where the input content timeline is being modified by a user exercising the transport controls of a digital video recorder (DVR). A Detector Engine receives decoded video frames and extracts a time-offset field, a VP1 payload, and a Cyclic Redundance Check (CRC) field in each video frame. A Content Timeline Tracker monitors and analyzes the output of the Detector Engine to produce a piecewise linear approximation of the content timeline, wherein playback rate changes by a user in an upstream device can be tracked. This enables the playback of auxiliary content which is synchronized to a watermark timeline recovered from the received content in cases where the recovered timeline has a non-linear mapping to real time. When the estimated speed is changing due to user-controlled trick play of recorded content, estimated speed deviates from the user intended speed profile because of imperfect playback of the media player. The system includes additional filtering of estimated speed to produce a Boolean updated speed which is asserted sparsely at estimated control segment endpoints in an attempt to delineate constant slope (constant speed) control segments.

    In-situ quantum error correction
    4.
    发明授权
    In-situ quantum error correction 有权

    公开(公告)号：US11651265B2

    公开(公告)日：2023-05-16

    申请号：US17401798

    申请日：2021-08-13

    Applicant: Google LLC

    Inventor： Julian Shaw Kelly

    IPC: G06F11/07 ,  G06F11/08 ,  G06N10/00 ,  H01L39/02 ,  G06N99/00 ,  H01L29/66

    CPC classification number: G06N10/00 ,  G06F11/0751 ,  G06F11/0787 ,  G06F11/08 ,  G06N99/00 ,  H01L29/66977 ,  H01L39/025

    Abstract: Methods, systems, and apparatus for parallel optimization of continuously running quantum error correction by closed-loop feedback. In one aspect, a method includes continuously and effectively optimizing qubit performance in-situ whilst an error correction operation on the quantum system is running. The method directly monitors the output from error detection and provides this information as feedback to calibrate the quantum gates associated with the quantum system. In some implementations, the physical qubits are spatially partitioned into one or more independent hardware patterns, where the errors attributable to each hardware pattern are non-overlapping. The one or more different sets of hardware patterns are then temporarily interleaved such that all physical qubits and operations are optimized. The method allows for the optimization of each section of a hardware pattern to be performed individually and in parallel, and can result is O(1) scaling.

    Hybrid forward error correction and replay technique for low latency
    10.
    发明授权
    Hybrid forward error correction and replay technique for low latency 有权

    公开(公告)号：US09979566B2

    公开(公告)日：2018-05-22

    申请号：US15277577

    申请日：2016-09-27

    Applicant: Intel Corporation

    Inventor： Brent R. Rothermel ,  Todd M. Rimmer

    IPC: G06F11/08 ,  G06F11/14 ,  H04L25/03 ,  H04L27/20

    CPC classification number: H04L25/03006 ,  G06F11/08 ,  G06F11/14 ,  H04L1/004 ,  H04L1/0047 ,  H04L1/1829

    Abstract: Disclosed herein are high performance systems with low latency error correction as well as related devices and methods. In some embodiments, high performance systems may include: central processing units, adapter chips, and switch chips connected via channels, each chip including link level forward error correction and link level replay, where errors at or below a threshold level are corrected by forward error correction and remaining errors are corrected using replay. In some embodiments, high performance systems may include: central processing units, adapter chips, and switch chips connected via channels, each chip including link level forward error correction, link level replay, and a multiplexer for determining which error correction technique to use based on the number of errors and an error threshold level.

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