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1.发明授权公开(公告)号：US10075170B2
公开(公告)日：2018-09-11
申请号：US15692024
申请日：2017-08-31
Applicant: The Charles Stark Draper Laboratory, Inc.
Inventor： Richard L. Vigeant , Antonio E. de la Serna
CPC classification number: H03K19/23 , G06F11/08 , G06F13/28 , G06F13/32 , G06F21/57 , G06F21/71 , G06F2211/1097 , G07C13/02 , H03K19/0813 , H03K25/02
Abstract: Circuits and methods for determining a majority vote from a plurality of inputs. An example circuit includes a voting input stage, a transfer stage, and an accumulating stage. The voting input stage includes at least three input switched capacitors. The transfer stage includes transfer switched capacitors corresponding to the input switched capacitors. The transfer switched capacitors charge a voting capacitor corresponding to each input switched capacitor during a state of a clock signal. The accumulating stage includes accumulating switched capacitors connecting the voting capacitors in series. The accumulating switched capacitors cause the charges of the voting capacitors to be accumulated during an alternate state of the clock signal. The accumulated charge of the voting capacitors represents a majority vote of the input switched capacitors.
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公开(公告)号：US20060176084A1
公开(公告)日：2006-08-10
申请号：US11333547
申请日：2006-01-18
Applicant: Hirohisa Suzuki , Kazuo Hasegawa , Eiji Akama
Inventor： Hirohisa Suzuki , Kazuo Hasegawa , Eiji Akama
IPC: G01R19/00
CPC classification number: H03K25/02
Abstract: An amplitude adjusting circuit comprises a first current mirror where a variable current of a variable current source is copied into each of 1st-3rd transistors; a second current mirror where the variable current is copied into each of 11th-13th transistors; a third current mirror having 6th-7th transistors where a current through the 2nd transistor copied from the variable current flows through the 6th transistor; a fourth current mirror having 8th-9th transistors where a current through the 12th transistor copied from the variable current flows through the 8th transistor; an inverter that has 1st-2nd conductivity type transistors and produces an output signal corresponding to a current level of the 7th or 9th transistor; a fifth current mirror having 15th-14th transistors where a current through the 14th transistor copied from the 15th transistor's becomes a current sourced by the 7th transistor; and a sixth current mirror having 5th-4th transistors where a current through the 4th transistor copied from the 5th transistor's becomes a current sunk by the 9th transistor.
Abstract translation: 振幅调整电路包括第一电流镜，其中可变电流源的可变电流被复制到第一至第三晶体管的每一个中; 第二电流镜，其中可变电流被复制到第十一至第十三晶体管的每一个中; 具有第六晶体管的第三电流镜，其中从可变电流复制的通过第二晶体管的电流流过第六晶体管; 具有第八晶体管的第四电流镜，其中从可变电流复制的第十二晶体管的电流流过第八晶体管; 具有第1〜第2导电型晶体管并产生与第7或第9晶体管的电流电平对应的输出信号的反相器; 具有第十五至第十四晶体管的第五电流镜，其中从第十五晶体管复制的通过第十四晶体管的电流变为由第七晶体管产生的电流; 以及具有第五至第四晶体管的第六电流镜，其中通过第五晶体管复制的第四晶体管的电流由第九晶体管成为电流。
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公开(公告)号：US4004163A
公开(公告)日：1977-01-18
申请号：US666116
申请日：1976-03-11
Applicant: John R. Spence
Inventor： John R. Spence
Abstract: A time delay circuit comprising an improved charge transfer scheme for use in a microelectronic circuit, such as, but not limited to, a calculator, and the like. The circuit efficiently charges a capacitance means with a signal to subsequently energize a utilization means. Sufficient time delay is provided when charging the capacitance means, after power is applied to the microelectronic chip means and before the utilization means is suitably energized, to insure that associated logic is first initialized and sources of reference potential are at proper operating levels.
Abstract translation: 包括用于微电子电路（例如但不限于计算器等）的改进的电荷转移方案的时间延迟电路。 电路有效地用信号对电容装置充电，随后使利用装置通电。 在对微电子芯片装置施加电力并且在利用装置被适当地通电之前对电容装置充电时，提供足够的时间延迟，以确保首先初始化相关联的逻辑并且参考电位源处于适当的操作电平。
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4.发明申请公开(公告)号：US20180074888A1
公开(公告)日：2018-03-15
申请号：US15692412
申请日：2017-08-31
Applicant: The Charles Stark Draper Laboratory, Inc.
Inventor： Richard L. Vigeant , Antonio E. de la Serna
CPC classification number: H03K19/23 , G06F11/08 , G06F13/28 , G06F13/32 , G06F21/57 , G06F21/71 , G06F2211/1097 , G07C13/02 , H03K19/0813 , H03K25/02
Abstract: Systems and methods for trusted integration of untrusted components. An example system includes at least three electrical components and voting (consensus) circuitry. The components have varied hierarchical implementations for providing common output given common input. The voting circuitry is configured to receive, as input, outputs from the components and provide a consensus output that is a majority of the outputs received from the components. Such a diversity of multiple untrusted system components (hardware and/or software) engaged in redundant operation can be integrated to as a consensus-based trusted system with a high degree of fault tolerance to unforeseen environmental interference, cyber-attack, supply chain counterfeit, inserted Trojan logic, or component design flaws. The degree of fault tolerance can be increased by increasing the degree of diversity of redundant operational nodes or by increasing the number of diversely implemented operational nodes.
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公开(公告)号：US20110170657A1
公开(公告)日：2011-07-14
申请号：US13119479
申请日：2009-09-15
Applicant: Christophe Mandier , Gilles Chammings , Bertrand Dupont , Michaël Tchagaspanian
Inventor： Christophe Mandier , Gilles Chammings , Bertrand Dupont , Michaël Tchagaspanian
IPC: H03K25/00
CPC classification number: H04N5/37455 , H03K25/02 , H04N5/33
Abstract: An analog counter includes, for at least one step, an input for receiving electric pulses and a means for modifying, by consecutive increments or decrements, a storage voltage for each received electrical pulse, a means for resetting the storage voltage, and a comparator for comparing the storage voltage with a threshold voltage and adapted to generate exceedance information. The counter further includes a control means adapted to control the resetting means in the event of the simultaneous detection of exceedance information from the comparator and of an input pulse.
Abstract translation: 对于至少一个步骤，模拟计数器包括用于接收电脉冲的输入和用于通过连续递增或递减修改每个接收到的电脉冲的存储电压的装置，用于重置存储电压的装置，以及用于 将存储电压与阈值电压进行比较，并适于产生超量信息。 该计数器还包括一个控制装置，适用于在同时检测来自比较器的超越信息和输入脉冲的情况下控制复位装置。
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Patent Agency Ranking
公开(公告)号：US07262650B2
公开(公告)日：2007-08-28
申请号：US11333547
申请日：2006-01-18
Applicant: Hirohisa Suzuki , Kazuo Hasegawa , Eiji Akama
Inventor： Hirohisa Suzuki , Kazuo Hasegawa , Eiji Akama
IPC: H03L5/00
CPC classification number: H03K25/02
Abstract: An amplitude adjusting circuit comprises a first current mirror where a variable current of a variable current source is copied into each of 1st-3rd transistors; a second current mirror where the variable current is copied into each of 11th-13th transistors; a third current mirror having 6th-7th transistors where a current through the 2nd transistor copied from the variable current flows through the 6th transistor; a fourth current mirror having 8th-9th transistors where a current through the 12th transistor copied from the variable current flows through the 8th transistor; an inverter that has 1st-2nd conductivity type transistors and produces an output signal corresponding to a current level of the 7th or 9th transistor; a fifth current mirror having 15th-14th transistors where a current through the 14th transistor copied from the 15th transistor's becomes a current sourced by the 7th transistor; and a sixth current mirror having 5th-4th transistors where a current through the 4th transistor copied from the 5th transistor's becomes a current sunk by the 9th transistor.
Abstract translation: 振幅调整电路包括第一电流镜，其中可变电流源的可变电流被复制到第一至第三晶体管的每一个中; 第二电流镜，其中可变电流被复制到第十一至第十三晶体管的每一个中; 具有第六晶体管的第三电流镜，其中从可变电流复制的通过第二晶体管的电流流过第六晶体管; 具有第八晶体管的第四电流镜，其中从可变电流复制的第十二晶体管的电流流过第八晶体管; 具有第1〜第2导电型晶体管并产生与第7或第9晶体管的电流电平对应的输出信号的反相器; 具有第十五至第十四晶体管的第五电流镜，其中从第十五晶体管复制的通过第十四晶体管的电流变为由第七晶体管产生的电流; 以及具有第五至第四晶体管的第六电流镜，其中通过第五晶体管复制的第四晶体管的电流由第九晶体管成为电流。
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7.发明申请公开(公告)号：US20180076815A1
公开(公告)日：2018-03-15
申请号：US15692024
申请日：2017-08-31
Applicant: The Charles Stark Draper Laboratory, Inc.
Inventor： Richard L. Vigeant , Antonio E. de la Serna
CPC classification number: H03K19/23 , G06F11/08 , G06F13/28 , G06F13/32 , G06F21/57 , G06F21/71 , G06F2211/1097 , G07C13/02 , H03K19/0813 , H03K25/02
Abstract: Circuits and methods for determining a majority vote from a plurality of inputs. An example circuit includes a voting input stage, a transfer stage, and an accumulating stage. The voting input stage includes at least three input switched capacitors. The transfer stage includes transfer switched capacitors corresponding to the input switched capacitors. The transfer switched capacitors charge a voting capacitor corresponding to each input switched capacitor during a state of a clock signal. The accumulating stage includes accumulating switched capacitors connecting the voting capacitors in series. The accumulating switched capacitors cause the charges of the voting capacitors to be accumulated during an alternate state of the clock signal. The accumulated charge of the voting capacitors represents a majority vote of the input switched capacitors.
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公开(公告)号：US20050285658A1
公开(公告)日：2005-12-29
申请号：US10880132
申请日：2004-06-29
Applicant: Kyle Schulmeyer , Lloyd Matthews , Bernard Pappert
Inventor： Kyle Schulmeyer , Lloyd Matthews , Bernard Pappert
CPC classification number: H03K25/02
Abstract: A voltage level shifting circuit (10) transitions an input signal at a first voltage to a second voltage higher than the first voltage. A cross-coupled latch provides the second voltage. Cascode configured transistors (16, 26) are connected in series with input transistors (18, 28) that receive the first voltage in complementary form. Capacitive devices (34, 40) are connected between the first voltage and gates of the cascode configured transistors for allowing independent small signal variations to occur on the gates of the cascode configured transistors for better control of duty cycle and rise and fall time matching of the level shifting circuit. Isolation devices (32, 38) permit independent modification of small signal voltages to occur on the gates of the cascode configured transistors.
Abstract translation: 电压电平移位电路（10）将第一电压的输入信号转换到高于第一电压的第二电压。 交叉耦合闩锁提供第二电压。 串联配置的晶体管（16,26）与以互补形式接收第一电压的输入晶体管（18,28）串联连接。 电容器件（34,40）连接在共源共栅配置的晶体管的第一电压和栅极之间，用于允许在共源共栅配置的晶体管的栅极上发生独立的小信号变化，以更好地控制占空比和上升和下降时间匹配 电平转换电路。 隔离装置（32,38）允许在共源共栅配置晶体管的栅极上发生小信号电压的独立修改。
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