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公开(公告)号：US12231134B2
公开(公告)日：2025-02-18
申请号：US18434225
申请日：2024-02-06
Applicant: Marvell Asia Pte, Ltd.
Inventor： Eitan Rosen , Oded Norman
Abstract: A circuit and corresponding method control cycle time of an output clock used to clock at least one other circuit. The circuit comprises an agile ring oscillator (ARO) and ARO controller. The ARO includes at least one instance of a first ring oscillator (RO) and second RO that generate high and low phases, respectively, of cycles of the output clock. The ARO controller controls durations of the high and low phases, independently, via first and second control words output to the ARO, respectively. In a present cycle of the output clock, the ARO controller effects a change to the high or low phase, or a combination thereof, in a next cycle of the output clock by updating the first or second control word, or a combination thereof, based on an indication of expected usage of the at least one other circuit in the next cycle. The change improves a performance-to-power ratio of the at least one other circuit.
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公开(公告)号：US11855636B2
公开(公告)日：2023-12-26
申请号：US17812813
申请日：2022-07-15
Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
Inventor： Yuxia Wang , Kai Tian
CPC classification number: H03K3/0315 , H03K3/011 , H03K3/017 , H03K3/3545 , H03L1/02 , H03L5/00
Abstract: Embodiments of the present application provide an oscillator and a clock generation circuit. The oscillator includes: a first ring topology, including a plurality of first inverters connected end to end, and configured to transmit an oscillation signal at a first transmission speed; and a second ring topology, including a plurality of second inverters connected end to end, and configured to transmit the oscillation signal at a second transmission speed, wherein the present application, the first ring topology is electrically connected to the second ring topology, and the second transmission speed is less than the first transmission speed.
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公开(公告)号：US11798784B2
公开(公告)日：2023-10-24
申请号：US16024602
申请日：2018-06-29
Applicant: Lam Research Corporation
Inventor： John C. Valcore, Jr. , Bradford J. Lyndaker
CPC classification number: H01J37/32091 , B44C1/22 , H01J37/32165 , H01J37/32935 , H03L5/00 , H05H2242/26
Abstract: Methods and apparatus for processing a substrate in a multi-frequency plasma processing chamber are disclosed. The base RF signal pulses between a high power level and a low power level. Each of the non-base RF generators, responsive to a control signal, proactively switches between a first predefined power level and a second predefined power level as the base RF signal pulses. Alternatively or additionally, each of the non-base RF generators, responsive to a control signal, proactively switches between a first predefined RF frequency and a second predefined RF frequency as the base RF signal pulses. Techniques are disclosed for ascertaining in advance of production time the first and second predefined power levels and/or the first and second predefined RF frequencies for the non-base RF signals.
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4.发明申请公开(公告)号：US20230043133A1
公开(公告)日：2023-02-09
申请号：US17903128
申请日：2022-09-06
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Nitin Agarwal , Aniruddha Roy , Preetham Narayana Reddy
Abstract: In an example, a system includes an oscillator circuit on a chip. The oscillator circuit includes a charging current generator including a current mirror and an amplifier, where the amplifier is coupled to a pin of the chip. The oscillator circuit also includes a first switch coupled to the pin, a second switch coupled to the pin and to a charging resistor, and a third switch coupled to the amplifier and an internal resistor, where the internal resistor is internal to the chip. The oscillator circuit includes a bias current source coupled to the current mirror. The system includes an external resistor coupled to the pin, where the external resistor is external to the chip. The system also includes an external capacitor coupled to the pin and coupled in parallel to the external resistor, where the external capacitor is external to the chip.
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公开(公告)号：US11496134B2
公开(公告)日：2022-11-08
申请号：US17349020
申请日：2021-06-16
Applicant: Efficient Power Conversion Corporation
Inventor： Edward Lee , Ravi Ananth
IPC: H03L5/00 , H03K5/22 , H03K19/0185 , H03K3/037
Abstract: A cross-coupled differential activated latch circuit with circuitry comprising a plurality of n-FETs and inverters that can be implemented completely in GaN. The circuitry prevents the digital latched values on the outputs of the latch from changing unless the digital input values on the inputs are different, thus preventing common-mode voltage on the inputs from corrupting the stored latch values.
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Patent Agency Ranking
公开(公告)号：US11349467B2
公开(公告)日：2022-05-31
申请号：US17647901
申请日：2022-01-13
Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
Inventor： Zhiqiang Zhang
Abstract: The present disclosure provides an offset voltage correction circuit and an offset voltage correction method, including: a data obtaining module, configured to receive a data signal and a reference signal, and obtain a data indicator signal based on a comparison result of the reference signal and an offset data signal, the offset data signal being a data signal superimposed with an offset signal; a trimming enable module, configured to receive the data signal, the reference signal, the data indicator signal and an enable signal, obtain a theoretical indicator signal based on a comparison result of the data signal and the reference signal if the enable signal is of a high level, and generate an enable flag signal based on a comparison result of the theoretical indicator signal and the data indicator signal; and an offset correction module, configured to cancel the offset signal based on the enable flag signal.
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公开(公告)号：US11159149B2
公开(公告)日：2021-10-26
申请号：US17021367
申请日：2020-09-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Soojung Rho , Jang-Woo Ryu , Hyunah An , Hangi Jung
Abstract: Disclosed is a level shifter. The level shifter includes a level shifting circuit, a first adjusting circuit, and a second adjusting circuit. The level shifting circuit determines whether to output a first current from a supply voltage line to an output node based on a voltage level of a first node and determines whether to output a second current from the supply voltage line to a third node based on a voltage level of a second node. The first adjusting circuit blocks an output of a third current from the third node to the first node when a clock signal having a first voltage level is received. The second adjusting circuit outputs a fourth current from the first node to a ground voltage line when the clock signal having the first voltage level is received.
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公开(公告)号：US11128300B1
公开(公告)日：2021-09-21
申请号：US16820659
申请日：2020-03-16
Applicant: Apple Inc.
Inventor： Nathan F. Hanagami , Hao Zhou , Jianbao Wang , Ruopeng Wang , Ludmil N. Nikolov
IPC: H03L5/00 , H03K19/0185 , H03K19/003 , H03K19/017 , H03K19/21 , H03K19/173
Abstract: A level shifter circuit with an intermediate power domain and method for operating the same is disclosed. The level shifter circuit includes an input circuit, an output circuit, and an intermediate circuit. The input circuit is coupled to receive an input signal from a first voltage domain operating according to a first supply voltage, and generates a first intermediate signal. The intermediate circuit receives the first intermediate signal and generates a second intermediate signal. The output circuit receives the intermediate signal and provides an output signal into a second voltage domain operating at a second supply voltage different from the first. A voltage multiplexer is configured to provide one of the first or second supply voltages to the intermediate circuit depending on a state of the input signal.
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公开(公告)号：US20210203228A1
公开(公告)日：2021-07-01
申请号：US16727759
申请日：2019-12-26
Applicant: Intel Corporation
Inventor： Xiaosen Liu , Krishnan Ravichandran , Harish Krishnamurthy , Vivek De
Abstract: A 3-level ripple quantization scheme provides power transistor (MOS) strength-tuning mechanism focused on the transient clamp period. The 3-level ripple quantization scheme solves the digital low dropout's (D-LDO's) tradeoff between silicon area (e.g., decoupling capacitor size), quiescent power consumption (e.g., speed of comparators), wide load range, and optimal output ripple. The 3-level ripple quantization scheme eliminates oscillation risk from either wide dynamic range or parasitic by exploiting asynchronous pulse patterns. As such, ripple magnitude for both fast di/dt loading events and various steady-state scenarios are shrunk effectively, resulting significant efficiency benefits.
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公开(公告)号：US11005419B2
公开(公告)日：2021-05-11
申请号：US16661245
申请日：2019-10-23
Applicant: Texas Instruments Incorporated
Inventor： Kunhee Cho , Danielle Griffith , James Murdock , Per Torstein Roine
IPC: H03B5/04 , H03B5/36 , H03B5/08 , H03B5/00 , H03B5/32 , H03L5/00 , H03L1/02 , H03L1/00 , H03L7/00 , H04W84/18
Abstract: A circuit includes an oscillator having a driver and a resonator. The driver receives a supply voltage at a supply input and provides a drive output to drive the resonator to generate an oscillator output signal. A power converter receives an input voltage and generates the supply voltage to the supply input of the driver. A temperature tracking device in the power converter controls the voltage level of the supply voltage to the supply input of the driver based on temperature such that the supply voltage varies inversely to the temperature of the circuit.
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