公开(公告)号：US20230412175A1

公开(公告)日：2023-12-21

申请号：US18247691

申请日：2021-12-07

Applicant: Analog Devices, Inc.

Inventor： Hyman Shanan ,  John Kenney

IPC: H03L7/099 ,  H03L1/02 ,  H03L7/189 ,  H04B1/16

CPC classification number: H03L7/099 ,  H03L1/02 ,  H03L7/189 ,  H04B1/16 ,  H03L2207/06

Abstract: Apparatus and methods for control and calibration of external oscillators are provided herein. In certain embodiments, an electronic oscillator system includes a semiconductor die and a controllable oscillator that is external to the semiconductor die. The oscillation frequency of the controllable oscillator is tuned by a first varactor and a second varactor. The semiconductor die includes a phase-locked loop (PLL) that provides fine tuning to the controllable oscillator by controlling the first varactor, and a calibration circuit that provides coarse tuning to the controllable oscillator by controlling the second varactor.

公开(公告)号：US20230387920A1

公开(公告)日：2023-11-30

申请号：US17751679

申请日：2022-05-24

Applicant: Airoha Technology Corp.

Inventor： Heng-Chih Lin ,  Shu-Yu Lin

IPC: H03L7/091 ,  H03L7/099 ,  H03L1/02

CPC classification number: H03L7/091 ,  H03L7/099 ,  H03L1/02

Abstract: A phase-locked loop (PLL) circuit includes a PLL core circuit, at least one lookup table, and a control circuit. The PLL core circuit generates an output clock under an open-loop calibration phase and a closed-loop calibration phase. The control circuit loads PLL parameters that are derived from the at least one lookup table to the PLL core circuit, performs open-loop calibration upon a first part of the PLL parameters under the open-loop calibration phase of the PLL core circuit, and performs closed-loop calibration upon a second part of the PLL parameters under the closed-loop calibration phase of the PLL core circuit.

公开(公告)号：US11722139B2

公开(公告)日：2023-08-08

申请号：US17575646

申请日：2022-01-14

Applicant: MEDIATEK INC.

Inventor： Chien-Wei Chen ,  Yu-Li Hsueh ,  Chao-Ching Hung

IPC: H03L7/02 ,  H03L7/099 ,  H03L7/00 ,  H03L1/02

CPC classification number: H03L7/02 ,  H03L1/02 ,  H03L7/00 ,  H03L7/0995

Abstract: A frequency-locked loop (FLL) and a method for correcting an oscillation frequency of an output signal of the FLL are provided. The FLL includes a switched capacitor circuit, a first resistor set, a second resistor set, a determination circuit and a control circuit. The switched capacitor circuit includes a capacitor, and connection of the capacitor is switched according to the oscillation frequency. The first resistor set is configured to provide a first resistance, and the second resistor set is configured to provide a second resistance. The determination circuit is configured to generate a determination result according to the first resistance and the second resistance. The control circuit is configured to generate a control signal for correcting the first resistance and the second resistance according to the determination result, where the oscillation frequency is determined based on the capacitor and at least one of the first resistance and the second resistance.

公开(公告)号：US20190149159A1

公开(公告)日：2019-05-16

申请号：US16189109

申请日：2018-11-13

Applicant: Seiko Epson Corporation

Inventor： Yasunori ONISHI ,  Shunsuke WATANABE ,  Yukihiro HASHI

IPC: H03L7/26 ,  H05K9/00 ,  H03B17/00 ,  H03L1/02

CPC classification number: H03L7/26 ,  G04F5/14 ,  H03B17/00 ,  H03L1/02 ,  H05K9/0007

Abstract: An atomic oscillator includes an atom cell that accommodates an alkali metal atom therein, a container that houses the atom cell, a substrate on which the container is disposed, and a thermally insulating mount that is fixed to the substrate and positions the container relative to the substrate.

公开(公告)号：US20180316355A1

公开(公告)日：2018-11-01

申请号：US15958311

申请日：2018-04-20

Applicant: SEIKO EPSON CORPORATION

Inventor： Takehiro YAMAMOTO

IPC: H03L3/00 ,  G06F1/04 ,  H03L1/02 ,  H03L5/02

CPC classification number: H03L3/00 ,  G06F1/04 ,  H03L1/02 ,  H03L5/02

Abstract: A circuit device includes a first oscillation circuit, a second oscillation circuit, a clock signal output circuit adapted to output a clock signal based on an output signal of the first oscillation circuit, and an output control circuit adapted to perform output control of the clock signal output circuit. The output control circuit includes a counter circuit adapted to perform a counting process based on an output signal of the second oscillation circuit, and the counter circuit outputs an output enable signal of the clock signal to the clock signal output circuit based on a result of the counting process.

公开(公告)号：US20180183413A1

公开(公告)日：2018-06-28

申请号：US15390397

申请日：2016-12-23

Applicant: ATI TECHNOLOGIES ULC ,  Advanced Micro Devices, Inc.

Inventor： Joyce Cheuk Wai Wong ,  Dragoljub Ignjatovic ,  Mikhail Rodionov ,  Ljubisa Bajic ,  Stephen V. Kosonocky ,  Steven J. Kommrusch

IPC: H03K3/013 ,  H03L7/099 ,  H03L5/00 ,  H03K5/15 ,  H03K5/1534 ,  H03K3/012

CPC classification number: H03K3/013 ,  H03K3/012 ,  H03K3/0231 ,  H03K3/03 ,  H03K5/1506 ,  H03K5/1508 ,  H03K5/1534 ,  H03L1/02 ,  H03L5/00 ,  H03L7/085 ,  H03L7/0997

Abstract: An output clock frequency of an adaptive oscillator circuit changes in response to noise on an integrated circuit power supply line. The circuit features two identical delay lines which are separately connected to a regulated supply and a droopy supply. In response to noise on the droopy supply, the delay lines cause a change in the output clock frequency. The adaptive oscillator circuit slows down the output clock frequency when the droopy supply droops or falls below the regulated supply. The adaptive oscillator circuit clamps the output clock frequency at a level determined by the regulated supply when the droopy supply overshoots or swings above the regulated supply.

公开(公告)号：US09998124B2

公开(公告)日：2018-06-12

申请号：US15369286

申请日：2016-12-05

Applicant: UNIVERSITY OF VIRGINIA PATENT FOUNDATION

Inventor： Benton H. Calhoun ,  Aatmesh Shrivastava

IPC: H03L1/02 ,  G06F1/32

CPC classification number: H03L1/026 ,  G06F1/04 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  H03B5/32 ,  H03K3/011 ,  H03K3/0315 ,  H03L1/02 ,  H03L1/021 ,  H03L1/022

Abstract: An ultra-low power clock source includes a compensated oscillator and an uncompensated oscillator coupled by a comparator circuit. In an example, the compensated oscillator is more stable than the uncompensated oscillator with respect to changes in one or more of temperature, voltage, age, or other environmental parameters. The uncompensated oscillator includes a configuration input configured to adjust an operating characteristic of the uncompensated oscillator. In an example, the uncompensated oscillator is adjusted using information from the comparator circuit about a comparison of output signals from the compensated oscillator and the uncompensated oscillator.

公开(公告)号：US20180115316A1

公开(公告)日：2018-04-26

申请号：US15335333

申请日：2016-10-26

Applicant: QUALCOMM Incorporated

Inventor： Ankit MAHESHWARI ,  Akash KUMAR ,  Rimal PATEL

IPC: H03L1/00 ,  H03L7/00 ,  H03B5/06 ,  H03B5/32 ,  G01R31/28

CPC classification number: H03L1/00 ,  G01R31/2849 ,  H03B5/06 ,  H03B5/32 ,  H03B2200/0082 ,  H03J7/04 ,  H03L1/02 ,  H03L1/028 ,  H03L7/00 ,  H04W76/27 ,  H04W88/02

Abstract: Techniques for calibrating a crystal oscillator of a wireless device are provided. A method according to these techniques includes operating a transmit path of the wireless device at a first carrier frequency, configuring a receive path of the wireless device to receive at a second carrier frequency, the second carrier frequency being offset from the first carrier frequency by a first frequency offset, transmitting a tone using the transmit path at a frequency that is offset from the first carrier frequency by a second frequency offset that is different than the first frequency offset, receiving a second tone via the receive path, and determining the oscillator error based on the second tone.

公开(公告)号：US09941888B2

公开(公告)日：2018-04-10

申请号：US15223435

申请日：2016-07-29

Applicant: Seiko Epson Corporation

Inventor： Kensaku Isohata ,  Takayuki Kikuchi ,  Takemi Yonezawa

IPC: H03B5/32 ,  H03L1/04 ,  H03L1/02 ,  H03B5/36

CPC classification number: H03L1/04 ,  H03B5/36 ,  H03L1/02 ,  H03L1/022 ,  H03L1/026 ,  H03L1/028

Abstract: An oscillator includes an oscillation source, multiple temperature control elements, and a controller adapted to perform control to suppress an increase in current consumed in one or more of the temperature control elements during at least part of a period from when operation of the oscillation source initiates to when the oscillation source reaches a specified temperature.

公开(公告)号：US09859021B2

公开(公告)日：2018-01-02

申请号：US14884601

申请日：2015-10-15

Applicant: RAMBUS INC.

Inventor： Yohan U. Frans ,  Wayne F. Ellis ,  Akash Bansal

IPC: G06F1/04 ,  G01R23/00 ,  G01R23/10 ,  G01R35/00 ,  G01D21/00 ,  G11C29/50 ,  G06F13/16 ,  G01R23/02 ,  G11C7/22 ,  G11C29/02 ,  H03L1/02 ,  G11C8/18 ,  G06F11/16 ,  G06F1/12 ,  G06F1/08 ,  G01R23/15 ,  G11C7/04

CPC classification number: G11C29/50012 ,  G01R23/02 ,  G01R23/15 ,  G01R35/005 ,  G06F1/08 ,  G06F1/12 ,  G06F11/1604 ,  G06F13/1689 ,  G11C7/04 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/18 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254 ,  H03L1/02

Abstract: The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit.