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公开(公告)号：US12019407B2
公开(公告)日：2024-06-25
申请号：US17911264
申请日：2021-03-16
Applicant: Oxford University Innovation Limited
Inventor： Andrew Briggs , Edward Laird , Kyriakos Porfyrakis
Abstract: An oscillation device, such as a frequency standard or “atomic clock”, is disclosed. The device comprises: a system capable of undergoing transitions between different energy states, the transitions defining at least a first resonance frequency and a second resonance frequency; an excitation device arranged to induce the system to undergo such transitions; a detection device arranged to detect a response of the system caused by the excitation device, to produce an output; and a controller arranged to receive the output, to control the excitation device to stimulate said transitions, and to obtain signals corresponding to at least the first and second resonance frequencies; wherein the controller is also arranged to process the obtained signals to produce a corrected output signal that is compensated against at least one influence on the resonance frequencies of the system.
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公开(公告)号：US20240106441A1
公开(公告)日：2024-03-28
申请号：US18466438
申请日：2023-09-13
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyung Min LEE , Gyu Sik KIM , Seung Jin KIM , Jae Hong JUNG
CPC classification number: H03L7/093 , G05F3/262 , H03L1/00 , H03L7/0995
Abstract: A phase locked loop circuit and a semiconductor device are provided. The phased locked loop circuit includes a reference current generator configured to generate a summed compensation current in which at least one of a process change, a temperature change or a power supply voltage change are compensated and output the summed compensation current as a reference current, a current digital-to-analog converter configured to convert the reference current into a control current in accordance with a digital code and a voltage control oscillator configured to generate a signal based on the control current, wherein the summed compensation current is based on weighted-averaging a first type compensation current and a second type compensation current in response to at least one of the process change, the temperature change or the power supply voltage change.
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公开(公告)号：US11909355B2
公开(公告)日：2024-02-20
申请号：US17942850
申请日：2022-09-12
Applicant: Apple Inc.
Inventor： Hongrui Wang , Abbas Komijani
CPC classification number: H03B5/12 , H03L1/00 , H04B1/40 , H03B2200/009 , H03B2200/0092 , H03B2201/038
Abstract: To prevent an undesired operating mode of voltage-controlled oscillation (VCO) circuitry from dominating a desired operating mode (e.g., an in-phase operating mode or an out-of-phase operating mode), a supply reset and ramp pulse may be provided to the VCO circuitry when switching to a new mode, such that supply voltage to the VCO circuitry is reset (e.g., set to 0 V or another reference voltage), and gradually increased or ramped up back to a steady-state voltage (e.g., used to maintain a mode) within a time duration. Additionally or alternatively, a switch control bootstrap pulse may be provided to the VCO circuitry that is bootstrapped to (e.g., applied instantaneously or concurrently with) switching the VCO circuitry to the new mode. After a time duration, the VCO circuitry may switch back to a steady-state voltage (e.g., used to maintain the new mode).
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公开(公告)号：US11811362B1
公开(公告)日：2023-11-07
申请号：US17983359
申请日：2022-11-08
Applicant: Cadence Design Systems, Inc.
Inventor： Alberto Baldisserotto , Aida Varzaghani
Abstract: Aspects of the present disclosure include systems and methods for temperature adaptive voltage controlled oscillators. In one example, a voltage controlled oscillator includes a cross junction circuit electrically coupled to a temperature dependent input current, and an inductor circuit electrically coupled to the cross junction circuit. The voltage controlled oscillator additionally includes a capacitor bank circuit electrically coupled to the inductor circuit, and an input node that receives a control voltage. The voltage controlled oscillator further includes an output node configured to provide an oscillation frequency output, wherein the oscillation frequency output is controlled by the control voltage.
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公开(公告)号：US11664765B2
公开(公告)日：2023-05-30
申请号：US17732832
申请日：2022-04-29
Applicant: Seiko Epson Corporation
Inventor： Takehiro Yamamoto
CPC classification number: H03B5/366 , H03B5/04 , H03B5/32 , H03B5/362 , H03L1/00 , H03B2200/009 , H03B2200/0034
Abstract: A circuit device includes an oscillation circuit configured to generate an oscillation signal, a first pre-driver disposed in a posterior stage of the oscillation circuit, a first output driver disposed in a posterior stage of the first pre-driver, a first regulator configured to supply a first regulated voltage to the first pre-driver, and a second regulator configured to supply a second regulated voltage to the first output driver, wherein the second regulator is shorter in transient response time than the first regulator.
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Patent Agency Ranking
公开(公告)号：US20180348506A1
公开(公告)日：2018-12-06
申请号：US15613455
申请日：2017-06-05
Applicant: STMicroelectronics Ltd
Inventor： Offir Duvdevany , Naomi Petrushevsky
CPC classification number: G02B26/0833 , G02B26/10 , G02B26/105 , H03L1/00 , H03L7/0814 , H04N9/3129 , H04N9/3135 , H04N9/3194
Abstract: Disclosed herein is a mirror controller for an oscillating mirror. The mirror controller includes a processor configured to receive a mirror sense signal from the oscillating mirror and to determine a phase error between the mirror sense signal and a mirror drive signal. The processor determines the phase error by sampling the mirror sense signal at a first time, sampling the mirror sense signal at a second time at which the mirror sense signal is expected to be equal to the mirror sense signal as sampled at the first time, and generating the phase error as a function of a difference between the sample of the mirror sense signal at the second time and the sample of the mirror sense signal at the first time.
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公开(公告)号：US10084462B2
公开(公告)日：2018-09-25
申请号：US15385266
申请日：2016-12-20
Applicant: SEIKO EPSON CORPORATION
Inventor： Takemi Yonezawa
CPC classification number: H03L7/095 , H03B5/32 , H03L1/00 , H03L1/026 , H03L7/091 , H03L7/099 , H03L7/181 , H03L2207/50
Abstract: A circuit device includes an oscillation signal generation circuit, a reference signal input terminal to which a reference signal is input, and an internal phase comparator that performs phase comparison between an input signal based on the oscillation signal and the reference signal. The oscillation signal generation circuit generates the oscillation signal using the frequency control data based on a result of the phase comparison from an external phase comparator which performs phase comparison between an input signal based on the oscillation signal and the reference signal in a first mode, and generates the oscillation signal using the frequency control data based on a result of the phase comparison from the internal phase comparator in a second mode.
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公开(公告)号：US10084459B2
公开(公告)日：2018-09-25
申请号：US15605267
申请日：2017-05-25
Applicant: Seiko Epson Corporation
Inventor： Akihiro Fukuzawa
IPC: H03L1/00
CPC classification number: H03L1/00
Abstract: An oscillator includes a control voltage generator that generates a control voltage between a first reference voltage and a second reference voltage with a digital signal, and a voltage controlled oscillation circuit that outputs a signal at a frequency in response to the control voltage. The control voltage generator includes a first D/A conversion circuit of resistor voltage-dividing type that generates a voltage between the first reference voltage and the second reference voltage.
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公开(公告)号：US20180248555A1
公开(公告)日：2018-08-30
申请号：US15445587
申请日：2017-02-28
Applicant: International Business Machines Corporation
Inventor： Keith A. Jenkins , Peilin Song , James H. Stathis , Franco Stellari
CPC classification number: H03L1/00 , G01R31/2824 , G01R31/2851 , H03B1/00 , H03B5/12 , H03B5/1215 , H03B5/30 , H03B5/36 , H03K3/0315 , H04L9/3278
Abstract: An electronic apparatus for testing an integrated circuit (IC) that includes a ring oscillator is provided. The apparatus configures the ring oscillator to produce oscillation at a first frequency and configures the ring oscillator to produce oscillation at a second frequency. The apparatus then compares the second frequency with an integer multiple of the first frequency to determine a resistive voltage drop between a voltage applied to the IC and a local voltage at the ring oscillator. The ring oscillator has a chain of inverting elements forming a long ring and a short ring. The ring oscillator also has an oscillation selection circuit that is configured to disable the short ring so that the ring oscillator produces a fundamental oscillation based on signal propagation through the long ring and enable the short ring so that the ring oscillator produces a harmonic oscillation based on a signal propagation through the short ring and the long ring.
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10.发明申请公开(公告)号：US20180138911A1
公开(公告)日：2018-05-17
申请号：US15354808
申请日：2016-11-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Feng Wei Kuo , Chewn-Pu Jou , Lan-Chou Cho , Huan-Neng Chen , Robert Bogden Staszewski , Seyednaser Pourmousavian
CPC classification number: H03L1/00 , H03K5/1515 , H03L7/091 , H03L7/0992 , H03L7/0995 , H03L2207/50
Abstract: An ADPLL circuit includes a time-to-digital converter (TDC) configured to generate a signal indicative of a phase difference between a first signal and a reference signal and a doubler electrically coupled to the TDC. The doubler is configured to receive a first voltage signal and generate a second voltage signal. The second voltage signal is provided to a voltage input of the TDC. The TDC is configured to generate one or more control signals for the doubler to adjust the second voltage signal.
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