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公开(公告)号：US12126348B2
公开(公告)日：2024-10-22
申请号：US18448319
申请日：2023-08-11
发明人： Florian Neveu
CPC分类号： H03L7/093 , H03L7/0893 , H03L7/099
摘要： In described examples, a phase locked loop (PLL) includes a compensation circuit, a transconductance circuit, and an oscillator. The compensation circuit includes a capacitor circuit and a resistive element having a resistance responsive to a center frequency of the PLL's bandwidth. The transconductance circuit includes a current source and an error amplifier. The current source generates a current responsive to the center frequency. The error amplifier has a transconductance responsive to the center frequency, and receives a signal responsive to the resistance and a difference between an input clock signal and a feedback signal. The oscillator input is coupled to the error amplifier output. The oscillator provides a signal at its output for generating the feedback signal.
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公开(公告)号：US12074568B2
公开(公告)日：2024-08-27
申请号：US17941767
申请日：2022-09-09
申请人： Apple Inc.
发明人： Hongrui Wang , Abbas Komijani
CPC分类号： H03B5/1228 , H03B5/1243 , H03L7/0891 , H03L7/093
摘要： Voltage-controlled oscillation circuitry includes multiple cores and multiple mode or gain boosters coupled between the multiple cores. To prevent an undesired operating mode of the voltage-controlled oscillation circuitry from dominating a desired operating mode (e.g., an in-phase operating mode or an out-of-phase operating mode), the mode boosters may increase a desired gain of the desired operating mode and decrease an undesired gain of the undesired operating modes. In particular, mode boosters coupled to terminals of the cores that are associated with the desired operating mode may be enabled, while mode boosters coupled to terminals of the cores that are associated with the undesired operating mode may be disabled.
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公开(公告)号：US20240275391A1
公开(公告)日：2024-08-15
申请号：US18110246
申请日：2023-02-15
申请人： Apple Inc.
发明人： Christian Venerus , Utku Seckin , Vikram Magoon
CPC分类号： H03L7/093 , H04L27/2082
摘要： This disclosure is directed to a transmitter including a phase locked loop (PLL), a modulator, and a power amplifier (PA). A controller including programmable and/or hardened logic circuitry may be coupled to the PLL and the modulator. The controller may provide encoded signals based on quadrature phase shift keying (QPSK) scheme for transmission by the transmitter. In particular, the controller may provide multiple bursts of pulses indicative of data packets to the modulator. Moreover, the controller may provide instructions indicative of generating clock signals with in-phase and quadrature phases to the PLL. The PLL may generate clock signals corresponding to the in-phase and quadrature phases. As such, the transmitter may generate in-phase and quadrature output signals based on receiving each burst of pulses with either in-phase or quadrature phases.
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公开(公告)号：US20240235561A9
公开(公告)日：2024-07-11
申请号：US17970477
申请日：2022-10-20
申请人： Intel Corporation
发明人： Hao Luo , Somnath Kundu , Brent R. Carlton
CPC分类号： H03L7/0992 , H03L7/093 , H03L2207/50
摘要： Embodiments herein relate to a sampling phase-locked loop (PLL) with a compensation circuit for reducing ripples due to the use of a fractional N divider. The compensation circuit includes a ripple amplifier and a ripple divider. The ripple amplifier receives an output voltage, Vmain, of a main sampling circuit of the PLL and amplifies its alternating current (AC) components. The amplified output voltage is provided to a ripple integrator which samples the minimum and maximum values to provide inputs to an operational amplifier (op amp). An output of the op amp is fed back to a digital-to-analog converter (DAC), which provides a corresponding compensation voltage, Vcomp. Vcomp is added to Vmain to provide a final output control voltage, Vctrl, to control a voltage-controlled oscillator (VCO) of the PLL.
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公开(公告)号：US20240223194A1
公开(公告)日：2024-07-04
申请号：US18205008
申请日：2023-06-02
发明人： Gary Qu Jin , Kamran Rahbar
CPC分类号： H03L7/093 , H03L7/07 , H03L7/0991
摘要： A phase lock system includes a phase detector to detect a phase difference between a reference signal and the output of a controllable oscillator circuit. A loop filter may filter the output of the loop filter and an integrator may integrate the output of the loop filter. The integrator output may be added to the output of the loop filter and may be input to the controllable oscillator circuit and may modify at least one of the phase and frequency of the controlled oscillator output. A loop filter may enable a 40 dB-per-decade roll-off and improve attenuation of reference signal noise and local oscillator noise.
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公开(公告)号：US20240213991A1
公开(公告)日：2024-06-27
申请号：US18604116
申请日：2024-03-13
CPC分类号： H03L7/0992 , H03B5/1212 , H03L7/093 , H03B2201/0208
摘要： A phase-locked loop comprises a voltage controlled oscillator. The voltage controlled oscillator comprises an inductor and a capacitor, connected in parallel, and also connected in parallel therewith, a negative resistance structure. A first terminal of the negative resistance structure is connected to respective first terminals of the inductor and the capacitor. A second terminal of the negative resistance structure is connected to respective second terminals of the inductor and the capacitor. The negative resistance structure exhibits a tunable capacitance, such that a frequency of an output of the voltage controlled oscillator can be tuned by a control input signal, and the control input signal is generated in the phase-locked loop. The negative resistance structure comprises first and second transistors.
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公开(公告)号：US12015415B1
公开(公告)日：2024-06-18
申请号：US18086565
申请日：2022-12-21
发明人： Sungmin Ock , Marzio Pedrali-Noy
CPC分类号： H03L7/093 , H03L7/0992
摘要： An apparatus including: a phase lock loop (PLL), including: a phase detector and loop pass filter (PD/LF), including: a phase/frequency detector including a first input configured to receive a reference signal, and a second input configured to receive a feedback signal, and an output configured to produce an output signal based on the reference and feedback signals; a first capacitor; and a charge pump, including: a charging path configured to generate a charging current to charge the first capacitor based on the output signal; and a discharging path including a first resistor configured to discharge the first capacitor.
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公开(公告)号：US20240178848A1
公开(公告)日：2024-05-30
申请号：US18518733
申请日：2023-11-24
申请人： LX SEMICON CO., LTD.
发明人： Jae Hwan LEE , Yoon Hoe KIM , Ji Hye KIM , Seung Chan JUNG , Hyun Soo CHUNG
CPC分类号： H03L7/083 , H03L7/093 , H03L7/1077
摘要： The present disclosure relates to a multi-chip clock synchronization device and a method capable of reducing an operating frequency and power consumption when a plurality of chips share clocks for multi-chip clock synchronization, which may include a reference clock supply unit connected to a plurality of chips and supplying a reference clock of a first frequency to each chip and a target clock generation unit generating a target clock of a second frequency based on the reference clock of the first frequency, wherein the reference clock supply unit may generate the reference clock of the first frequency which is N times lower than the second frequency of the target clock to supply the generated reference clock to each chip, and the target clock generation unit may multiply the first frequency of the reference clock by N times when the reference clock of the first frequency is input to generate the target clock of the second frequency.
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公开(公告)号：US20240137028A1
公开(公告)日：2024-04-25
申请号：US17992701
申请日：2022-11-22
发明人： Animesh PAUL
CPC分类号： H03L7/087 , H03L7/093 , H03L7/0991
摘要： In an example, a phase-locked loop (PLL) circuit includes an oscillator, a frequency search circuit, and an analog control loop. The oscillator is configured to provide a clock signal. The frequency search circuit is configured to measure a first frequency of the clock signal for a first clock control signal, measure a second frequency of a second signal for a second clock control signal, and determine, based on the first frequency, the second frequency, the first clock control signal, and the second clock control signal, a third clock control signal corresponding to a programmed frequency, the third clock control signal for causing the clock signal to have a frequency based on the programmed frequency. The analog control loop is configured to control the oscillator to cause the frequency to converge to the programmed frequency.
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公开(公告)号：US20240085973A1
公开(公告)日：2024-03-14
申请号：US18514807
申请日：2023-11-20
申请人： Intel Corporation
CPC分类号： G06F1/3296 , G01R19/2513 , H03K5/24 , H03K19/20 , H03L7/093 , H03L7/095
摘要： An apparatus and method are described, which prior to an event that could result in frequency overshoot, sends a signal to a voltage regulator or generator requesting a temporary supply voltage and/or current boost. This enables a clocking source, such as a phase locked loop (PLL) to lock fast while not needing any long-term voltage guard bands. The apparatus and scheme allows for on-the-fly change in supply voltage and/or clock frequency for a processor with little to no impact on Vmin. During the clock frequency overshoot, the supply voltage is temporarily boosted and then reduced down to the expected voltage level of the power supply. Such boost allows for absorbing the clock frequency overshoot impact. The supply voltage level can be reduced in a step-wise fashion to avoid any potential undershoot in clock frequency.
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