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3409 条记录 (耗时 0.026 秒)

    ENCODER
    1.
    发明公开
    ENCODER 审中-公开

    公开(公告)号：US20240356562A1

    公开(公告)日：2024-10-24

    申请号：US18635948

    申请日：2024-04-15

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Win-San Khwa ,  Hiroki Noguchi ,  Ku-Feng Lin

    IPC分类号： H03M7/16 ,  G11C11/16 ,  H03K19/20

    CPC分类号： H03M7/16 ,  G11C11/1673 ,  H03K19/20

    摘要： An encoding system may be provided. The encoding system may comprise a first stage and a second stage. The first stage may be configured to receive a first input, decode the first input, and produce a first output comprising the decoded first input. The second stage may be configured to receive a second input, receive the first output from the first stage, and convert the first input and the second input from a first coding system to a second coding system based on the second input and the first output. The second stage may produce a second output comprising the converted first input and the converted second input.

    Bias unit element with binary weighted charge transfer lines
    3.
    发明授权
    Bias unit element with binary weighted charge transfer lines 有权

    公开(公告)号：US12118331B2

    公开(公告)日：2024-10-15

    申请号：US17163588

    申请日：2021-02-01

    申请人： Ceremorphic, Inc.

    发明人： Martin Kraemer ,  Ryan Boesch ,  Wei Xiong

    IPC分类号： G06F7/544 ,  G06F17/16 ,  H03K19/20 ,  H03M1/38

    CPC分类号： G06F7/5443 ,  G06F17/16 ,  H03K19/20 ,  H03M1/38

    摘要： A Bias Unit Element (UE) comprises NAND gates with complementary outputs, the complementary outputs coupled through a charge transfer capacitor to a differential charge transfer bus comprising positive charge transfer lines and negative charge transfer lines. Each line of the differential charge transfer bus has a particular binary weighted line weight, such as 1, 2, 4, 2, 4, 8, and 4, 8, 16. Digital bias inputs are provided to the Bias UE NAND gate inputs, with a clear bit to initialize charge, and a sign input for enabling one of a positive Bias UE or negative Bias UE. A low-to-high transition causes a transfer of charge to the binary weighted charge transfer bus, thereby adding or subtracting a bias value from the charge transfer bus.

    Monotonic Hybrid Capacitor Digital-To-Analog Converter
    6.
    发明公开
    Monotonic Hybrid Capacitor Digital-To-Analog Converter 审中-公开

    公开(公告)号：US20240313800A1

    公开(公告)日：2024-09-19

    申请号：US18348422

    申请日：2023-07-07

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Aidong Yin ,  Shenggao Li ,  Paul Ranucci

    IPC分类号： H03M1/80 ,  H03K19/20

    CPC分类号： H03M1/802 ,  H03K19/20

    摘要： A monotonic capacitor digital-to-analog converter (CDAC) is provided. The CDAC includes a converter array comprising a plurality of CDAC units, wherein each CDAC unit comprises a logic unit, a switch, and a capacitor, and wherein each logic unit comprises a first input, a second input, and a third input. The CDAC further includes a first set of control lines, and each of the first set of control lines is connected to the first inputs of the logic units of the CDAC units in a corresponding column of the converter array. The CDAC further includes a second set of control lines, and each of the second set of control lines is connected to the second inputs of the logic units of the CDAC units in a corresponding row of the converter array, but is disconnected from the second input of the logic unit of a CDAC unit in the corresponding row and the last column of the converter array. Each of the second set of control lines is further connected to the third inputs of the logic units of the CDAC units in a row of the converter array adjacent to the corresponding row.

    Storage device and method of discharging an operating voltage
    7.
    发明授权
    Storage device and method of discharging an operating voltage 有权

    公开(公告)号：US12087349B2

    公开(公告)日：2024-09-10

    申请号：US17862472

    申请日：2022-07-12

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Kyoungeun Lee ,  Hyunjoon Yoo ,  Seunghan Lee

    IPC分类号： G11C5/14 ,  G11C11/4074 ,  G11C11/4099 ,  G11C16/30 ,  H03K19/20

    CPC分类号： G11C11/4074 ,  G11C5/147 ,  G11C11/4099 ,  G11C16/30 ,  H03K19/20 ,  G11C5/145

    摘要： A storage device includes: a controller that exchanges data with a host through an interface; memory devices that store the data; a power supply circuit that outputs internal voltages, required for the controller and the memory devices, using an external voltage received through the interface; a distribution circuit that provides an operating voltage to the memory devices; and a discharge circuit including a first comparator that compares a first internal voltage, among the internal voltages, with a reference voltage and a second comparator that compares a second internal voltage, different from the first internal voltage, with the reference voltage, and including an operating circuit that computes an output of the first comparator and an output of the second comparator to output a discharge control signal determining whether the operating voltage has been discharged.

    ADDER CIRCUIT USING LOOKUP TABLES
    8.
    发明公开
    ADDER CIRCUIT USING LOOKUP TABLES 审中-公开

    公开(公告)号：US20240281212A1

    公开(公告)日：2024-08-22

    申请号：US18588604

    申请日：2024-02-27

    申请人： Achronix Semiconductor Corporation

    发明人： Christopher C. LaFrieda ,  Virantha N. Ekanayake

    IPC分类号： G06F7/575 ,  G06F1/03 ,  G06F7/504 ,  H03K19/20 ,  H03K19/21

    CPC分类号： G06F7/575 ,  G06F1/03 ,  G06F7/5045 ,  H03K19/20 ,  H03K19/21

    摘要： A four-input lookup table (“LUT4”) is modified to operate in a first mode as an ordinary LUT4 and in a second mode as a 1-bit adder providing a sum output and a carry output. A six-input lookup table (“LUT6”) is modified to operate in a first mode as an ordinary LUT6 with a single output and in a second mode as a 2-bit adder providing a sum output and a carry output. Both possible results for the two different possible carry inputs can be determined and selected between when the carry input is available, implementing a 2-bit carry-select adder when in the second mode and retaining the ability to operate as an ordinary LUT6 in the first mode. Using the novel LUT6 design in a circuit chip fabric allows a 2-bit adder slice to be built that efficiently makes use of the LUT6 without requiring additional logic blocks.

    NON-BINARY COMPUTER USING ALTERNATING CURRENT
    10.
    发明公开
    NON-BINARY COMPUTER USING ALTERNATING CURRENT 审中-公开

    公开(公告)号：US20240267047A1

    公开(公告)日：2024-08-08

    申请号：US18635889

    申请日：2024-04-15

    申请人： 6GCO Ltd.

    发明人： Gagan Garg ,  Anindya Bose

    IPC分类号： H03K17/687 ,  G06F1/26 ,  H03K19/20

    CPC分类号： H03K17/687 ,  G06F1/26 ,  H03K19/20

    摘要： An integrated circuit for a computer may include a non-binary logic gate circuit configured to perform a logic operation that includes: at least one input terminal; an output terminal; and transistor circuitry configured to: receive, via the at least one input terminal, at least one alternating current (AC) input voltage at three input voltage levels, wherein each of the three input voltage levels corresponds to a respective one of three logic values; and generate, at the output terminal, an output voltage at one or more output voltage levels based on the at least one AC input voltage and the logic operation, wherein each of the one or more output voltage levels corresponds to a respective one of the three logic values.