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公开(公告)号：US12068284B2
公开(公告)日：2024-08-20
申请号：US17537026
申请日：2021-11-29
发明人： Tzu-Hsien Yang , Hiroki Noguchi , Mahmut Sinangil , Yih Wang
IPC分类号： H01L25/18 , H01L25/065 , H01L21/768
CPC分类号： H01L25/0657 , H01L25/18 , H01L21/76898 , H01L2225/06544
摘要： A 3D IC structure includes multiple dies, such as a top die and a bottom die. The top die and/or the bottom die can each include devices such as computing units, Analog-to-Digital converters, analog circuits, RF circuits, logic circuits, sensors, Input/Output devices, and/or memory devices. One or more vertical interconnect structure (VIS) cells are formed adjacent one or more sides of the device. A VIS is formed in some or all of the VIS cells. One or more non-sensitive circuits, such as repeaters, diodes, and/or passive circuits (e.g., resistors, inductors, capacitors, transformers), are disposed in at least one VIS cell.
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2.发明公开公开(公告)号：US20230298665A1
公开(公告)日：2023-09-21
申请号：US18300706
申请日：2023-04-14
发明人： Perng-Fei Yuh , Yih Wang , Ku-Feng Lin , Jui-Che Tsai , Hiroki Noguchi , Fu-An Wu
IPC分类号： G11C14/00 , G11C11/419 , G11C11/16
CPC分类号： G11C14/0081 , G11C11/161 , G11C11/1659 , G11C11/1675 , G11C11/419
摘要： Disclosed herein is an integrated circuit including multiple magnetic tunneling junction (MTJ) cells coupled to a static random access memory (SRAM). In one aspect, the integrated circuit includes a SRAM having a first port and a second port, and a set of pass transistors coupled to the first port of the SRAM. In one aspect, the integrated circuit includes a set of MTJ cells, where each of the set of MTJ cells is coupled between a select line and a corresponding one of the set of pass transistors.
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公开(公告)号：US20230273752A1
公开(公告)日：2023-08-31
申请号：US18313374
申请日：2023-05-08
发明人： Hiroki Noguchi , Shih-Lien Linus Lu , Yu-Der Chih , Yih Wang
CPC分类号： G06F3/0659 , G06F1/28 , G06F3/0604 , G06F3/0673 , G06F9/4893
摘要： A memory device including a memory array with a plurality of memory macros, a power supplying circuit, and a controller is provided. The power supplying circuit is coupled to the memory array. The controller is coupled to the memory array. The power supplying circuit is configured to provide power to perform write operations to a number of the memory macros at the same time. The number of the memory macros for the write operations performed at the same time is not higher than a maximum number of the memory macros. The controller obtains the maximum number of the memory macros for the write operations performed at the same time by the power supplying circuit. The controller re-arranges a schedule for a sequence of the write operations of the memory macros to generate a re-arranged schedule. The maximum number is taken as a threshold value. In the re-arranged schedule, a number of part of the memory macros for the write operations performed at the same time is equal to or less then the threshold value.
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公开(公告)号：US20230206963A1
公开(公告)日：2023-06-29
申请号：US18177749
申请日：2023-03-02
发明人： Hiroki Noguchi , Ku-Feng Lin , Yih Wang
IPC分类号： G11C7/06
CPC分类号： G11C7/062
摘要： A sensing amplifier, coupled to at least one memory cell, includes an output terminal and a reference terminal, a multiplexer circuit, and a plurality of reference cells having equal value. An output terminal of the multiplexer circuit is coupled to the reference terminal of the sensing amplifier. Each of the reference cell is coupled to each input node of the multiplexer circuit. The multiplexer circuit is controlled by a control signal to select one of the reference cells as a selected reference cell to couple to the reference terminal of the sensing amplifier when each read operation to the at least one memory cell is performed. The plurality of reference cells are selected sequentially and repeatedly, and the one of the reference cells is selected for one read operation to the at least one memory cell.
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公开(公告)号：US20230188159A1
公开(公告)日：2023-06-15
申请号：US18165025
申请日：2023-02-06
发明人： Win-San Khwa , Hiroki Noguchi , Ku-Feng Lin
CPC分类号： H03M7/16 , G11C11/1673 , H03K19/20
摘要： An encoding system may be provided. The encoding system may comprise a first stage and a second stage. The first stage may be configured to receive a first input, decode the first input, and produce a first output comprising the decoded first input. The second stage may be configured to receive a second input, receive the first output from the first stage, and convert the first input and the second input from a first coding system to a second coding system based on the second input and the first output. The second stage may produce a second output comprising the converted first input and the converted second input.
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6.发明授权公开(公告)号：US11657873B2
公开(公告)日：2023-05-23
申请号：US17409341
申请日：2021-08-23
发明人： Perng-Fei Yuh , Yih Wang , Ku-Feng Lin , Jui-Che Tsai , Hiroki Noguchi , Fu-An Wu
IPC分类号： G11C14/00 , G11C11/419 , G11C11/16
CPC分类号： G11C14/0081 , G11C11/161 , G11C11/1659 , G11C11/1675 , G11C11/419
摘要： Disclosed herein is an integrated circuit including multiple magnetic tunneling junction (MTJ) cells coupled to a static random access memory (SRAM). In one aspect, the integrated circuit includes a SRAM having a first port and a second port, and a set of pass transistors coupled to the first port of the SRAM. In one aspect, the integrated circuit includes a set of MTJ cells, where each of the set of MTJ cells is coupled between a select line and a corresponding one of the set of pass transistors.
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公开(公告)号：US20220302088A1
公开(公告)日：2022-09-22
申请号：US17537026
申请日：2021-11-29
发明人： Tzu-Hsien Yang , Hiroki Noguchi , Mahmut Sinangil , Yih Wang
IPC分类号： H01L25/065 , H01L25/18
摘要： A 3D IC structure includes multiple dies, such as a top die and a bottom die. The top die and/or the bottom die can each include devices such as computing units, Analog-to-Digital converters, analog circuits, RF circuits, logic circuits, sensors, Input/Output devices, and/or memory devices. One or more vertical interconnect structure (VIS) cells are formed adjacent one or more sides of the device. A VIS is formed in some or all of the VIS cells. One or more non-sensitive circuits, such as repeaters, diodes, and/or passive circuits (e.g., resistors, inductors, capacitors, transformers), are disposed in at least one VIS cell.
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公开(公告)号：US11189356B2
公开(公告)日：2021-11-30
申请号：US16803202
申请日：2020-02-27
发明人： Yih Wang , Hiroki Noguchi
IPC分类号： G11C17/00 , G11C17/12 , G11C17/16 , H01L21/8234 , G11C11/408 , G11C11/4094 , G11C11/4074
摘要： Various one-time-programmable (OTP) memory cells are disclosed. An OTP memory cell includes an additional dopant region that extends at least partially under the gate of a transistor, such as an anti-fuse transistor. The additional dopant region provides an additional current path for a read current. Alternatively, an OTP memory cell includes three transistors; an anti-fuse transistor and two select transistors. The two select transistors can be configured as a cascaded select transistor or as two separate select transistors.
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公开(公告)号：US12041855B2
公开(公告)日：2024-07-16
申请号：US18227867
申请日：2023-07-28
CPC分类号： H10N50/80 , G11C11/1655 , G11C11/1657 , H10N50/01 , H10N50/85
摘要： A magnetic memory device includes a magnetic tunnel junction (MTJ) stack, a spin-orbit torque (SOT) induction wiring disposed over the MTJ stack, a first terminal coupled to a first end of the SOT induction wiring, a second terminal coupled to a second end of the SOT induction wiring, and a selector layer coupled to the first terminal.
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公开(公告)号：US11854656B2
公开(公告)日：2023-12-26
申请号：US17817898
申请日：2022-08-05
发明人： Hiroki Noguchi
CPC分类号： G11C7/1051 , G06F11/1068 , G11C7/06 , G11C7/1096
摘要： Performing refresh operation in a memory device is provided. A refresh operation without address rotation is performed in a cell array of the memory device. Performing the refresh operation without address rotation is repeated for a predetermined number of times. After repeating performing the refresh operation with address rotation for the predetermined number of times, a refresh operation with address rotation is performed in the cell array.
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