公开(公告)号：US20240315147A1

公开(公告)日：2024-09-19

申请号：US18677654

申请日：2024-05-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ji-Feng YING ,  Jhong-Sheng WANG ,  Tsann LIN

IPC: H10N50/80 ,  G11C11/16 ,  H01F10/32 ,  H10B61/00 ,  H10N50/01 ,  H10N50/85 ,  H10N52/80

CPC classification number: H10N50/80 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1675 ,  H01F10/3254 ,  H01F10/329 ,  H10B61/22 ,  H10N50/01 ,  H10N50/85 ,  H10N52/80

Abstract: A magnetic memory includes a first spin-orbital-transfer-spin-torque-transfer (SOT-STT) hybrid magnetic device disposed over a substrate, a second SOT-STT hybrid magnetic device disposed over the substrate, and a SOT conductive layer connected to the first and second SOT-STT hybrid magnetic devices. Each of the first and second SOT-STT hybrid magnetic devices includes a first magnetic layer, as a magnetic free layer, a spacer layer disposed under the first magnetic layer, and a second magnetic layer, as a magnetic reference layer, disposed under the spacer layer. The SOT conductive layer is disposed over the first magnetic layer of each of the first and second SOT-STT hybrid magnetic devices.

公开(公告)号：US12035636B2

公开(公告)日：2024-07-09

申请号：US18140472

申请日：2023-04-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Ji-Feng Ying ,  Jhong-Sheng Wang ,  Tsann Lin

IPC: H10N50/10 ,  G11C11/16 ,  H01F10/32 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85 ,  H10N52/80

CPC classification number: H10N50/80 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1675 ,  H01F10/3254 ,  H01F10/329 ,  H10B61/22 ,  H10N50/01 ,  H10N50/85 ,  H10N52/80

Abstract: A magnetic memory includes a first spin-orbital-transfer-spin-torque-transfer (SOT-STT) hybrid magnetic device disposed over a substrate, a second SOT-STT hybrid magnetic device disposed over the substrate, and a SOT conductive layer connected to the first and second SOT-STT hybrid magnetic devices. Each of the first and second SOT-STT hybrid magnetic devices includes a first magnetic layer, as a magnetic free layer, a spacer layer disposed under the first magnetic layer, and a second magnetic layer, as a magnetic reference layer, disposed under the spacer layer. The SOT conductive layer is disposed over the first magnetic layer of each of the first and second SOT-STT hybrid magnetic devices.

公开(公告)号：US12027224B2

公开(公告)日：2024-07-02

申请号：US17654998

申请日：2022-03-16

Applicant: International Business Machines Corporation

Inventor： Julien Frougier ,  Kangguo Cheng ,  Ruilong Xie

IPC: G11C29/44 ,  G11C11/16 ,  G11C29/02 ,  G11C29/12 ,  G11C29/24 ,  G06F12/1018 ,  G11C29/18

CPC classification number: G11C29/4401 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C29/024 ,  G11C29/1201 ,  G11C29/24 ,  G06F12/1018 ,  G11C2029/1802 ,  G11C2029/4402

Abstract: Embodiments disclosed herein include a semiconductor device. The semiconductor device may include a magnetoresistive random access memory (MRAM) array. The MRAM array may include defective MRAM cells, redundancy MRAM cells, and operational MRAM cells. The semiconductor device may also include an address input electrically connected to the MRAM array and a selector circuit wired to the address input and an output of the MRAM array. The selector circuit may be configured to read the defective MRAM cells to identify the MRAM array.

公开(公告)号：US20240212771A1

公开(公告)日：2024-06-27

申请号：US18601100

申请日：2024-03-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chih-Min LIU

IPC: G11C17/18 ,  G11C11/16 ,  G11C17/16

CPC classification number: G11C17/18 ,  G11C11/1673 ,  G11C17/16 ,  G11C11/161 ,  G11C11/1659

Abstract: A circuit includes a plurality of anti-fuse cells coupled to a first selection circuit, a plurality of magnetic random-access memory (MRAM) cells coupled to a second selection circuit, an amplifier including a first input terminal coupled to each of the first and second selection circuits, an analog-to-digital converter (ADC) including input terminals coupled to output terminals of the amplifier, and a comparator including a first input port coupled to an output port of the ADC. The amplifier, ADC, and comparator are configured to output data bits from the comparator responsive to current levels received from the first selection circuit at the first input terminal of the amplifier and first voltage levels received from the second selection circuit at the first input terminal of the amplifier.

公开(公告)号：US20240203472A1

公开(公告)日：2024-06-20

申请号：US18589540

申请日：2024-02-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Fa-Shen Jiang ,  Hsia-Wei Chen ,  Hsun-Chung Kuang ,  Hai-Dang Trinh ,  Cheng-Yuan Tsai

IPC: G11C11/16 ,  G11C11/56 ,  H10B53/30 ,  H10B61/00 ,  H10B63/00

CPC classification number: G11C11/161 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/5614 ,  G11C11/5657 ,  G11C11/5678 ,  H10B53/30 ,  H10B61/22 ,  H10B63/30

Abstract: Various embodiments of the present disclosure are directed towards a memory device. The memory device has a first transistor having a first source/drain and a second source/drain, where the first source/drain and the second source/drain are disposed in a semiconductor substrate. A dielectric structure is disposed over the semiconductor substrate. A first memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the first memory cell has a first electrode and a second electrode, where the first electrode of the first memory cell is electrically coupled to the first source/drain of the first transistor. A second memory cell is disposed in the dielectric structure and over the semiconductor substrate, where the second memory cell has a first electrode and a second electrode, where the first electrode of the second memory cell is electrically coupled to the second source/drain of the first transistor.

公开(公告)号：US11941299B2

公开(公告)日：2024-03-26

申请号：US17745839

申请日：2022-05-16

Applicant: Integrated Silicon Solution, (Cayman) Inc.

Inventor： Benjamin Louie ,  Neal Berger ,  Lester Crudele

IPC: G06F3/06 ,  G11C11/16 ,  G11C29/00

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/0673 ,  G11C11/1659 ,  G11C11/1693 ,  G11C29/846 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1677

Abstract: Embodiments of the present invention facilitate efficient and effective increased memory cell density configuration. In one embodiment, a memory system comprises: an array of addressable memory cells, wherein the addressable memory cells of the array comprise magnetic random access memory (MRAM) cells and wherein further the array is organized into a plurality of banks; an engine configured to control access to the addressable memory cells organized into the plurality of banks; and a pipeline configured to perform access control and communication operations between the engine and the array of addressable memory cells. At least a portion of operations associated with accessing at least a portion of one of the plurality of memory banks via the pipeline are performed substantially concurrently or in parallel with at least a portion of operations associated with accessing at least another portion of one of the plurality of memory banks via the pipeline.

公开(公告)号：US11935620B2

公开(公告)日：2024-03-19

申请号：US17353592

申请日：2021-06-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yue-Der Chih ,  Cheng-Hsiung Kuo ,  Gu-Huan Li ,  Chien-Yin Liu

IPC: G11C16/04 ,  G11C5/02 ,  G11C7/20 ,  G11C11/16 ,  G11C11/406 ,  G11C13/00

CPC classification number: G11C7/20 ,  G11C5/02 ,  G11C11/1659 ,  G11C11/1677 ,  G11C11/406 ,  G11C13/0033 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0076

Abstract: A memory device for memory cell programming and erasing with refreshing operation is disclosed. The memory device includes multiple location-related memory cells and a refresh module. The location-related memory cells are coupled to a bit line on which a selecting voltage is applied. The refresh module rewrites a stored data of a first cell of the location-related memory cells to the first cell of the location-related memory cells in response to an operation count being smaller than a number N. N is related to the number of the location-related memory cells.

公开(公告)号：US11929105B2

公开(公告)日：2024-03-12

申请号：US17504005

申请日：2021-10-18

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Baolei Wu ,  Xiaoguang Wang ,  Yulei Wu

IPC: G11C11/00 ,  G11C11/16 ,  H10B61/00 ,  H10N50/80

CPC classification number: G11C11/1675 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  H10B61/22 ,  H10N50/80

Abstract: The present application makes public a magnetic memory and a reading/writing method thereof, which magnetic memory comprises at least one cell layer, and the cell layer includes a plurality of parallel second wires that are disposed in a second plane, the first plane being parallel to the second plane, and projections of the second wires onto the first plane intercrossing the first wires; a plurality of storage elements that are disposed between the first plane and the second plane, the storage elements including magnetic tunnel junctions and bi-directional gating components connected in series along a direction perpendicular to the first plane, the magnetic tunnel junctions being connected to the first wires, the bi-directional gating components being connected to the second wires, and the bi-directional gating components being configured to be conductive upon application of a threshold voltage and/or a threshold current.

公开(公告)号：US11894037B2

公开(公告)日：2024-02-06

申请号：US17718759

申请日：2022-04-12

Applicant: SanDisk Technologies LLC

Inventor： Michael Grobis ,  James W. Reiner ,  Michael Nicolas Albert Tran ,  Juan P. Saenz ,  Gerrit Jan Hemink

IPC: G11C13/00 ,  G11C11/16 ,  G11C7/20 ,  H01L25/065 ,  H01L23/00 ,  H01L25/18

CPC classification number: G11C11/1659 ,  G11C7/20 ,  G11C13/003 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/1443

Abstract: In a memory array with a cross-point structure, at each cross-point junction a programmable resistive memory element, such as an MRAM memory cell, is connected in series with a threshold switching selector, such as an ovonic threshold switch. The threshold switching selector switches to a conducting state when a voltage above a threshold voltage is applied. When powered down for extended periods, the threshold voltage can drift upward. If the drift is excessive, this can make the memory cell difficult to access and can disturb stored data values when accessed. Techniques are presented to determine whether excessive voltage threshold drift may have occurred, including a read based test and a time based test. Techniques are also presented for initializing a cross-point array, for both first fire and cold start, by using voltage levels shifted from half-select voltage levels used in a standard memory access.

公开(公告)号：US11889703B2

公开(公告)日：2024-01-30

申请号：US17975242

申请日：2022-10-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan Kyung Kim ,  Eun Ji Lee ,  Ji Yean Kim ,  Tae Seong Kim ,  Jae Wook Joo

IPC: H10B61/00 ,  G11C11/16 ,  H10N50/10

CPC classification number: H10B61/20 ,  G11C11/1659 ,  G11C11/1673 ,  H10N50/10

Abstract: A magnetic junction memory device is provided. The magnetic junction memory device including a sensing circuit including a sensing node, the sensing node being connected to a first end of a transistor and configured to change a voltage of the sensing node in accordance with a resistance of a magnetic junction memory cell, a gating voltage generator circuit configured to generate a gating voltage of the transistor using a reference resistor and a reference voltage, and a read circuit configured to read data from the magnetic junction memory cell using the reference voltage and the voltage of the sensing node.