公开(公告)号：US20250072302A1

公开(公告)日：2025-02-27

申请号：US18721012

申请日：2022-12-22

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  WEEBIT NANO LTD

Inventor： Jean-Baptiste DORY ,  Gabriel MOLAS ,  Jean-François NODIN ,  Anthonin VERDY

IPC: H10N70/20 ,  H10B63/00 ,  H10N70/00

Abstract: An assembly includes at least two non-volatile resistive memories arranged electrically in parallel to one another and each being electrically connected in series to a selector layer respectively forming at least two selectors, each one assigned to one of the memories, the assembly including two upper electrodes which both extend over the selector layer and which are electrically insulated from each other, one of the resistive memories extending against a lateral surface of the first upper electrode and another of the resistive memories extending against a lateral surface of the second upper electrode.

公开(公告)号：US20250068022A1

公开(公告)日：2025-02-27

申请号：US18810808

申请日：2024-08-21

Applicant: Dmitri Pescianschi

Inventor： Dmitri Pescianschi

IPC: G02F1/1365 ,  H10B63/00 ,  H10N70/20

Abstract: An active-matrix liquid crystal display (AM LCD), which uses controlled resistors with memory instead of capacitors as memory elements for pixels. The voltage control on the liquid crystal cell is performed by means of a voltage divider on the controlled resistors.

公开(公告)号：US12237267B2

公开(公告)日：2025-02-25

申请号：US17586740

申请日：2022-01-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Liang Cheng

IPC: H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H10B12/00 ,  H10B51/20 ,  H10B61/00 ,  H10B63/00

Abstract: A semiconductor device includes a first transistor formed on a first side of a substrate. The semiconductor device includes a first power rail structure vertically disposed over the first transistor, a second power rail structure vertically disposed over the first power rail structure, and a memory portion vertically disposed over the second power rail structure. The first power rail structure, and a second power rail structure, and the memory portion are all disposed on a second side of the substrate opposite to the first side.

公开(公告)号：US20250063955A1

公开(公告)日：2025-02-20

申请号：US18721840

申请日：2022-12-06

Applicant: ZHEJIANG HIKSTOR TECHNOLOGY CO., LTD

Inventor： Zhimeng YU ,  Shikun HE

IPC: H10N70/00 ,  H10B61/00 ,  H10B63/00 ,  H10N50/01

Abstract: Disclosed in the present application are a memory and a method for manufacturing thereof. The manufacturing method includes: bottom electrodes of a memory array region and a first portion of top contact body of a logic region are formed on an upper surface of a bottom circuit layer simultaneously; a patterned dielectric layer is formed on an upper surface of a memory cell layer in the memory array region and the logic region; hard masks and a second portion of top contact body are formed in a via of the patterned dielectric layer simultaneously, where the hard masks corresponds to the bottom electrodes, and the second portion of top contact body is connected to the first portion of top contact body in a contact manner; and the memory cell layer is etched to form memory cells.

公开(公告)号：US12232435B2

公开(公告)日：2025-02-18

申请号：US18130184

申请日：2023-04-03

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Franck Arnaud ,  David Galpin ,  Stephane Zoll ,  Olivier Hinsinger ,  Laurent Favennec ,  Jean-Pierre Oddou ,  Lucile Broussous ,  Philippe Boivin ,  Olivier Weber ,  Philippe Brun ,  Pierre Morin

IPC: H10B63/00 ,  G11C13/00 ,  H10N70/00 ,  H10N70/20

Abstract: An integrated circuit includes a substrate with an active area, a first insulating layer, a second insulating layer, and a phase-change material. The integrated circuit further includes a heating element in an L-shape, with a long side in direct physical contact with the phase-change material and a short side in direct physical contact with a via. The heating element is surrounded by first, second, and third insulating spacers, with the first insulating spacer having a planar first sidewall in contact with the long side of the heating element, a convex second sidewall, and a planar bottom face in contact with the short side of the heating element. The second and third insulating spacers are in direct contact with the first insulating spacer and the long side of the heating element.

公开(公告)号：US12232335B2

公开(公告)日：2025-02-18

申请号：US17890837

申请日：2022-08-18

Applicant: Hefei Reliance Memory Limited

Inventor： Zhichao Lu ,  Brent Steven Haukness

IPC: H10N70/20 ,  G11C7/12 ,  G11C13/00 ,  H10B63/00 ,  H10N70/00

Abstract: Disclosed is a resistive random access memory (RRAM). The RRAM includes a bottom electrode made of tungsten and a switching layer made of hafnium oxide disposed above the bottom electrode, wherein the switching layer includes a switchable filament. The RRAM further includes a resistive layer disposed above the switching layer and a bit line disposed above the resistive layer, wherein the resistive layer extends laterally to connect two or more memory cells along the bit line.

公开(公告)号：US20250056814A1

公开(公告)日：2025-02-13

申请号：US18796880

申请日：2024-08-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seulji Song ,  Hodae Kim ,  Woojun Jeong

IPC: H10B63/00 ,  H10N70/00

Abstract: A memory device includes a first conductive line, a second conductive line, and a memory cell disposed between the first and second conductive lines. The memory cell includes a lower electrode layer, a switching pattern, and an upper electrode layer. The switching pattern includes a main region including a pair of first side walls and a pair of second walls, and a corner region at four corners of the main region. The switching pattern includes a chalcogenide layer including a Group VI chalcogen element, an element of Group IV and an element of Group V, and the concentration of the Group IV element in the corner region is greater than that of the Group IV element in the main region, or the concentration of the Group V element in the corner region is greater than that of the Group V element in the main region.

公开(公告)号：US12225833B2

公开(公告)日：2025-02-11

申请号：US18164125

申请日：2023-02-03

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Hiroyuki Miyazoe ,  Eduard Albert Cartier ,  Babar Khan ,  Youngseok Kim ,  Dexin Kong ,  Soon-Cheon Seo ,  Joel P. De Souza

IPC: H10N70/00 ,  H10B63/00

Abstract: Embodiments of the invention provide a resistive switching device that includes a metal interconnect electrode and a charge-particle-treated memory stack over the metal interconnect electrode. The charge-particle-treated memory stack includes a plurality of layers that includes a top electrode, a bottom electrode, and a dielectric layer between the top electrode and the bottom electrode. The dielectric layer includes a portion of a blanket dielectric layer. The bottom electrode includes a portion of a blanket bottom electrode layer. The charge-particle-treated memory stack further includes a current-conducting filament characteristic that results from charge particle treatments applied while a top surface of the blanket dielectric layer is exposed and a top surface of the blanket bottom electrode is exposed.

公开(公告)号：US20250048942A1

公开(公告)日：2025-02-06

申请号：US18926326

申请日：2024-10-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chao-I Wu

IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

Abstract: Memory devices and methods of forming the same are provided. A memory device includes a substrate, a first conductive layer, a phase change layer, a selector layer and a second conductive layer. The first conductive layer is disposed over the substrate. The phase change layer is disposed over the first conductive layer. The selector layer is disposed between the phase change layer and the first conductive layer. The second conductive layer is disposed over the phase change layer. In some embodiments, at least one of the phase change layer and the selector layer has a narrow-middle profile.

公开(公告)号：US20250048941A1

公开(公告)日：2025-02-06

申请号：US18925068

申请日：2024-10-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Chao Lin ,  Carlos H. Diaz ,  Shao-Ming Yu ,  Tung-Ying Lee

IPC: H10N70/20 ,  H01L23/528 ,  H10B41/10 ,  H10B61/00 ,  H10B63/00 ,  H10B63/10 ,  H10N70/00

Abstract: Provided are a memory cell and a method of forming the same. The memory cell includes a bottom electrode, an etching stop layer, a variable resistance layer, and a top electrode. The etching stop layer is disposed on the bottom electrode. The variable resistance layer is embedded in the etching stop layer and in contact with the bottom electrode. The top electrode is disposed on the variable resistance layer. A semiconductor device having the memory cell is also provided.