公开(公告)号：US20240365567A1

公开(公告)日：2024-10-31

申请号：US18471585

申请日：2023-09-21

申请人： Samsung Electronics Co., Ltd.

发明人： Jinwoo Lee ,  Dongho Ahn ,  Jin Myung Choi

IPC分类号： H10B63/00

CPC分类号： H10B63/845 ,  H10B63/34

摘要： A semiconductor device according to an embodiment includes a gate stack structure and a channel structure. The gate stack structure includes a plurality of gate electrodes and a plurality of insulating layers alternately stacked on a substrate in a first direction perpendicular to an upper surface of the substrate. The channel structure includes a portion penetrating through the gate stack structure and extending in the first direction. The channel structure includes a channel layer, a resistance change layer, and a metal-containing layer sequentially stacked. The metal-containing layer includes a metal or a metal compound.

公开(公告)号：US20240357838A1

公开(公告)日：2024-10-24

申请号：US18763239

申请日：2024-07-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chao-I Wu ,  Yu-Ming Lin

IPC分类号： H10B63/00 ,  H10N70/00

CPC分类号： H10B63/845 ,  H10B63/34 ,  H10N70/066

摘要： A three-dimensional memory device includes a stacking structure, memory pillars, and conductive pillars. The stacking structure includes stacking layers stacked along a vertical direction, each stacking layer including a gate layer, a gate dielectric layer, and a channel layer. The gate layer, the gate dielectric layer, and the channel layer extend along a horizontal direction, and the gate dielectric layer is disposed between the gate layer and the channel layer. The memory pillars extend along the vertical direction and are laterally separated and in contact with the channel layer of each stacking layer. Each memory pillar comprises a first electrode, a second electrode, and a switching layer between the first and second electrodes. The conductive pillars extend along the vertical direction and are laterally separated and in contact with the channel layer of each stacking layer. The memory pillars and the conductive pillars are alternately arranged along the horizontal direction.

公开(公告)号：US20240355685A1

公开(公告)日：2024-10-24

申请号：US18650718

申请日：2024-04-30

申请人： Micron Technology, Inc.

发明人： Amitava Majumdar ,  Radhakrishna Kotti ,  Mallesh Rajashekharaiah

IPC分类号： H01L21/66 ,  G11C13/00 ,  H01J37/04 ,  H01J37/28 ,  H01L21/768 ,  H01L23/528 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC分类号： H01L22/12 ,  H01J37/28 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/5283 ,  H10B63/84 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/71 ,  H01J37/04 ,  H01J2237/2804 ,  H01J2237/2814 ,  H10N70/231 ,  H10N70/826 ,  H10N70/8825

摘要： Methods, systems, and devices for electron beam probing techniques and related structures are described to enable inline testing of memory device structures. Conductive loops may be formed, some of which may be grounded and others of which may be electrically floating in accordance with a predetermined pattern. The loops may be scanned with an electron beam and image analysis techniques may be used to generate an optical pattern. The generated optical pattern may be compared to an expected optical pattern, which may be based on the predetermined pattern of grounded and floating loops. An electrical defect may be determined based on any difference between the generated optical pattern and the expected optical pattern. For example, if a second loop appears as having a brightness corresponding to a grounded loop, this may indicate that an unintended short exists. Fabrication techniques may be adjusted for subsequent devices to correct identified defects.

公开(公告)号：US12127489B2

公开(公告)日：2024-10-22

申请号：US18170947

申请日：2023-02-17

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Tai-Yen Peng ,  Hui-Hsien Wei ,  Wei-Chih Wen ,  Pin-Ren Dai ,  Chien-Min Lee ,  Han-Ting Tsai ,  Jyu-Horng Shieh ,  Chung-Te Lin

IPC分类号： H10B63/00 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N70/00 ,  H10N70/20

CPC分类号： H10N70/884 ,  H10B61/22 ,  H10B63/30 ,  H10B63/82 ,  H10B63/84 ,  H10N50/01 ,  H10N50/80 ,  H10N70/023 ,  H10N70/063 ,  H10N70/24 ,  H10N70/245 ,  H10N70/826 ,  H10N70/8416 ,  H10N70/8833

摘要： An IC structure comprises a substrate, a first dielectric structure, a second dielectric structure, a first via structure, and a memory cell structure. The substrate comprises a memory region and a logic region. The first dielectric structure is over the memory region. The second dielectric structure laterally extends from the first dielectric structure to over the logic region. The second dielectric structure has a thickness less than a thickness of the first dielectric structure. The first via structure extends through the first dielectric structure. A top segment of the first via structure is higher than a top surface of the first dielectric structure. The first memory cell structure is over the first via structure.

公开(公告)号：US12127485B2

公开(公告)日：2024-10-22

申请号：US17421418

申请日：2020-01-07

申请人： NANOBRIDGE SEMICONDUCTOR, INC.

发明人： Naoki Banno ,  Munehiro Tada ,  Hideaki Numata ,  Koichiro Okamoto

IPC分类号： H01L27/24 ,  H10B63/00 ,  H10N70/00

CPC分类号： H10N70/023 ,  H10B63/30 ,  H10N70/063 ,  H10N70/8416 ,  H10N70/883

摘要： A switching element that has reduced switching voltage and leakage current and that demonstrates high reliability and low power consumption is achieved as a result of comprising: a first insulation layer in which first wiring mainly consisting of copper is embedded in a first wiring groove that opens upward; a second insulation layer which is formed on an upper surface of the first insulation layer and the first wiring and has an opening that reaches the first insulation layer and the first wiring; a first electrode which is the portion of the first wiring that is exposed from the opening; an oxygen supply layer which is formed on an upper surface of the second insulation layer, generates oxygen plasma during etching to form the opening in the second insulation layer, and remains at least in the vicinity of the opening of the upper surface of the second insulation layer; an ion conducting layer which is formed on the upper surface of the first insulation layer and the first electrode that are exposed from the opening, an inner surface of the opening of the second insulation layer, and an upper surface of the oxygen supply layer; and a second electrode that is formed on an upper surface of the ion conducting layer.

公开(公告)号：US12119055B2

公开(公告)日：2024-10-15

申请号：US17329028

申请日：2021-05-24

申请人： Micron Technology, Inc.

发明人： Hernan A. Castro ,  Everardo Torres Flores ,  Jeremy M. Hirst

IPC分类号： G11C13/00 ,  G11C5/02 ,  G11C5/06 ,  H10B63/00 ,  G11C8/08 ,  H10N70/00 ,  H10N70/20

CPC分类号： G11C13/0004 ,  G11C5/025 ,  G11C5/063 ,  G11C13/0023 ,  H10B63/24 ,  H10B63/30 ,  H10B63/80 ,  H10B63/84 ,  G11C8/08 ,  G11C2213/71 ,  G11C2213/77 ,  H10N70/231 ,  H10N70/826 ,  H10N70/8828

摘要： Row electrode drivers and column electrode drivers for a memory device are distributed within a footprint share by a memory cell array.

公开(公告)号：US20240334847A1

公开(公告)日：2024-10-03

申请号：US18738161

申请日：2024-06-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-Chieh Huang ,  Jieh-Jang Chen ,  Feng-Jia Shiu ,  Chern-Yow Hsu

IPC分类号： H10N70/00 ,  H01L21/285 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/321 ,  H01L21/768 ,  H10B63/00 ,  H10N70/20

CPC分类号： H10N70/8418 ,  H01L21/28562 ,  H01L21/28568 ,  H01L21/31053 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/76879 ,  H10B63/80 ,  H10N70/021 ,  H10N70/063 ,  H10N70/231 ,  H10N70/826 ,  H10N70/8413 ,  H10N70/8828 ,  H10N70/8833

摘要： A method includes providing a substrate having a conductive column, a dielectric layer over the conductive column, and a plurality of sacrificial blocks over the dielectric layer, the plurality of sacrificial blocks surrounding the conductive column from a top view; depositing a sacrificial layer covering the plurality of sacrificial blocks, the sacrificial layer having a dip directly above the conductive column; depositing a hard mask layer over the sacrificial layer; removing a portion of the hard mask layer from a bottom of the dip; etching the bottom of the dip using the hard mask layer as an etching mask, thereby exposing a top surface of the conductive column; and forming a conductive material inside the dip, the conductive material being in physical contact with the top surface of the conductive column.

公开(公告)号：US20240334714A1

公开(公告)日：2024-10-03

申请号：US18459191

申请日：2023-08-31

申请人： SK hynix Inc.

发明人： Sang Gu YEO ,  Yong Jin JEONG

IPC分类号： H10B63/00 ,  H01L21/762

CPC分类号： H10B63/845 ,  H01L21/76224

摘要： A manufacturing method may include forming an opening within a stack, forming a variable resistance layer within the opening and on the stack, forming a conductive layer on the variable resistance layer, forming a conductive pattern including a first part within the opening and a second part on the stack, by etching the conductive layer, forming a variable resistance pattern including a first part within the opening and a second part on the stack, by etching the variable resistance layer, and planarizing the conductive pattern and the variable resistance pattern until the stack is exposed.

公开(公告)号：US20240324477A1

公开(公告)日：2024-09-26

申请号：US18593589

申请日：2024-03-01

申请人： Kioxia Corporation

发明人： Soichiro ONO ,  Hiroyuki KANAYA

IPC分类号： H10N70/00 ,  H10B63/00

CPC分类号： H10N70/841 ,  H10B63/84 ,  H10N70/011 ,  H10N70/8828

摘要： A storage device includes a memory cell that includes a variable resistance storage element and a switching element connected in series thereto and stacked therewith in a first direction, the switching element including a first electrode, a second electrode that includes a first part formed of a first material to which a first element is added, and a switching material layer that is between the first electrode and the first part of the second electrode and formed of a first insulating material to which the first element is added. The storage device further includes a first insulating layer that surrounds the switching material layer and formed of the first insulating material to which the first element is not added. An outer periphery of the first part of the second electrode and an outer periphery of the switching material layer are aligned in the first direction.

公开(公告)号：US20240324474A1

公开(公告)日：2024-09-26

申请号：US18735715

申请日：2024-06-06

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yu-Der CHIH ,  Wen-Zhang LIN ,  Yun-Sheng CHEN ,  Jonathan Tsung-Yung CHANG ,  Chrong-Jung LIN ,  Ya-Chin KING ,  Cheng-Jun LIN ,  Wang-Yi LEE

IPC分类号： H10N70/00 ,  H10B63/00

CPC分类号： H10N70/021 ,  H10B63/80 ,  H10N70/063 ,  H10N70/066 ,  H10N70/068 ,  H10N70/841

摘要： A resistive memory device includes a bottom electrode, a top electrode and a resistance changing element. The top electrode is disposed above and spaced apart from the bottom electrode, and has a downward protrusion aligned with the bottom electrode. The resistance changing element covers side and bottom surfaces of the downward protrusion.