公开(公告)号：US12144269B2

公开(公告)日：2024-11-12

申请号：US17948712

申请日：2022-09-20

Applicant: HEFEI RELIANCE MEMORY LIMITED

Inventor： Liang Zhao ,  Zhichao Lu

IPC: H10N70/00 ,  H10B63/00

Abstract: Thermal field controlled electrical conductivity change devices and applications therefore are provided. In some embodiments, a thermal switch, comprises: a metal-insulator-transition (MIT) material; first and second terminals electrically coupled to the MIT material; and a heater disposed near the MIT material.

公开(公告)号：US11950519B2

公开(公告)日：2024-04-02

申请号：US17540486

申请日：2021-12-02

Applicant: HEFEI RELIANCE MEMORY LIMITED

Inventor： Zhiqiang Wei ,  Zhichao Lu

IPC: H10N70/00 ,  G11C13/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: H10N70/253 ,  G11C13/0002 ,  H10B63/30 ,  H10N70/011 ,  H10N70/061 ,  H10N70/8265 ,  H10N70/841 ,  H10N70/883

Abstract: A non-volatile memory cell includes a bottom electrode, a top electrode having a conductive material, a resistive layer interposed between the bottom electrode and the top electrode, and side portions covering sides of the top electrode and the resistive layer. The side portions contain an oxide of the conductive material. The non-volatile memory cell further includes a contact wire disposed on the top electrode. A width of the contact wire is less than a width between lateral outer surfaces of the side portions.

公开(公告)号：US11735262B2

公开(公告)日：2023-08-22

申请号：US17698808

申请日：2022-03-18

Applicant: Hefei Reliance Memory Limited

Inventor： Brent Haukness ,  Zhichao Lu

IPC: G11C13/00 ,  G11C11/56

CPC classification number: G11C13/0069 ,  G11C11/56 ,  G11C13/004 ,  G11C13/0028 ,  G11C13/0061 ,  G11C2013/0045 ,  G11C2013/0076 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/79

Abstract: A method and related apparatus for using an indication of RRAM cell resistance to determine a write condition are disclosed. A cell characteristic of an RRAM cell may be determined to a higher bit resolution than a data read value. A write condition may be selected for the RRAM cell, based on the cell characteristic. The RRAM cell may be written to, using the selected write condition.

公开(公告)号：US11653580B2

公开(公告)日：2023-05-16

申请号：US17230273

申请日：2021-04-14

Applicant: Hefei Reliance Memory Limited

Inventor： Zhichao Lu ,  Gary Bela Bronner

IPC: H01L21/00 ,  H01L45/00 ,  G11C13/00

CPC classification number: H01L45/08 ,  G11C13/0007 ,  G11C13/0011 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/14 ,  H01L45/143 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1641 ,  G11C2213/50 ,  G11C2213/51

Abstract: Disclosed is a resistive random access memory (RRAM). The RRAM includes a bottom electrode made of tungsten and a switching layer made of hafnium oxide disposed above the bottom electrode, wherein the switching layer includes a filament and one or more lateral regions including a doping material that are between a top region and a bottom region of the switching layer. The RRAM further includes a top electrode disposed above the switching layer.

公开(公告)号：US11557264B2

公开(公告)日：2023-01-17

申请号：US16842385

申请日：2020-04-07

Applicant: HEFEI RELIANCE MEMORY LIMITED

Inventor： Liang Zhao ,  Zhichao Lu ,  Zhigang Han

IPC: G09G5/00 ,  G11C7/10 ,  H04N5/57

Abstract: Circuitry for adjusting luminance of a display device is provided. The circuitry includes a non-volatile memory array having a plurality memory cells configured to store luminance data of the display device, and a luminance adjusting circuit configured to receive image data to be displayed on the display device. The luminance adjusting circuit is coupled directly to the non-volatile memory array to receive the luminance data of the display device from the non-volatile memory array and adjust the image data based on the luminance data of the display device.

公开(公告)号：US11302394B2

公开(公告)日：2022-04-12

申请号：US17081092

申请日：2020-10-27

Applicant: Hefei Reliance Memory Limited

Inventor： Brent Haukness ,  Zhichao Lu

IPC: G11C13/00 ,  G11C11/56

Abstract: A method and related apparatus for using an indication of RRAM cell resistance to determine a write condition are disclosed. A cell characteristic of an RRAM cell may be determined to a higher bit resolution than a data read value. A write condition may be selected for the RRAM cell, based on the cell characteristic. The RRAM cell may be written to, using the selected write condition.

公开(公告)号：US12142241B2

公开(公告)日：2024-11-12

申请号：US18083355

申请日：2022-12-16

Applicant: HEFEI RELIANCE MEMORY LIMITED

Inventor： Liang Zhao ,  Zhichao Lu ,  Zhigang Han

IPC: G09G5/00 ,  G11C7/10 ,  H04N5/57

Abstract: Circuitry for adjusting luminance of a display device is provided. The circuitry includes a non-volatile memory array having a plurality memory cells configured to store luminance data of the display device, and a luminance adjusting circuit configured to receive image data to be displayed on the display device. The luminance adjusting circuit is coupled directly to the non-volatile memory array to receive the luminance data of the display device from the non-volatile memory array and adjust the image data based on the luminance data of the display device.

公开(公告)号：US12027206B2

公开(公告)日：2024-07-02

申请号：US17948419

申请日：2022-09-20

Applicant: Hefei Reliance Memory Limited

Inventor： Zhichao Lu ,  Brent Haukness ,  Gary Bronner

IPC: G11C13/00 ,  G11C29/12

CPC classification number: G11C13/0069 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/0064 ,  G11C29/12 ,  G11C2013/0073 ,  G11C2013/0083

Abstract: The embodiments herein describe technologies of initializing resistive memory devices (e.g., non-volatile and volatile memory devices). In one method, a first voltage is applied across a resistance change material of a memory cell to form an initial filament and multiple cycles are performed to condition the initial filament. Each of the multiple cycles includes: applying a second voltage with a first polarity across the resistance change material; and applying a third voltage with a second polarity across the resistance change material.

公开(公告)号：US11462585B2

公开(公告)日：2022-10-04

申请号：US16994993

申请日：2020-08-17

Applicant: Hefei Reliance Memory Limited

Inventor： Zhichao Lu ,  Brent Steven Haukness

IPC: H01L27/24 ,  H01L45/00 ,  G11C7/12 ,  G11C13/00

Abstract: Disclosed is a resistive random access memory (RRAM). The RRAM includes a bottom electrode made of tungsten and a switching layer made of hafnium oxide disposed above the bottom electrode, wherein the switching layer includes a switchable filament. The RRAM further includes a resistive layer disposed above the switching layer and a bit line disposed above the resistive layer, wherein the resistive layer extends laterally to connect two or more memory cells along the bit line.

公开(公告)号：US10998044B2

公开(公告)日：2021-05-04

申请号：US16462721

申请日：2017-12-19

Applicant: Hefei Reliance Memory Limited

Inventor： Brent Haukness ,  Zhichao Lu

IPC: G11C13/00

Abstract: An RRAM array has one or more source lines and one or more bitlines. A control circuit sets an RRAM cell to a low resistance state in a set operation, and resets the RRAM cell to a high resistance state in a reset operation. A voltage applied to a bitline or source line is ramped during a first time interval, held to a maximum voltage value during a second interval, and ceased after the second time interval.