公开(公告)号：US10381366B1

公开(公告)日：2019-08-13

申请号：US15898571

申请日：2018-02-17

申请人： SANDISK TECHNOLOGIES LLC

发明人： Yuji Takahashi ,  Satoru Mayuzumi ,  Vincent Shih

IPC分类号： H01L27/11556 ,  H01L27/102 ,  H01L27/06 ,  H01L45/00 ,  G11C16/04 ,  H01L21/822

CPC分类号： H01L27/11556 ,  G11C16/0441 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/1021 ,  H01L45/143 ,  H01L45/144

摘要： A memory device includes first conductive rails laterally extending along a first horizontal direction over a substrate, a rectangular array of first memory pillar structures, each containing a memory element, overlying top surfaces of the first conductive rails, second conductive rails laterally extending along a second horizontal direction and overlying top surfaces of the rectangular array of first memory pillar structures, and a one-dimensional array of first cavities free of solid material portions therein, laterally extending along the second horizontal direction and located between neighboring pairs of the second conductive rails.

公开(公告)号：US20190148456A1

公开(公告)日：2019-05-16

申请号：US16226855

申请日：2018-12-20

申请人： Samsung Electronics Co., Ltd.

发明人： Zhe Wu ,  Dong-ho Ahn ,  Hideki Horii ,  Soon-oh Park ,  Jeong-hee Park ,  Jin-woo Lee ,  Dong-jun Seong ,  Seol Choi

IPC分类号： H01L27/24 ,  H01L45/00

CPC分类号： H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1675

摘要： A memory device includes a plurality of word lines extending along a first direction and spaced apart from each other along a second direction that is perpendicular to the first direction; a plurality of bit lines extending along the second direction and spaced apart from each other in the first direction, the plurality of bit lines being spaced apart from the plurality of word lines in a third direction that is perpendicular to both the first and second directions; and a plurality of memory cells being respectively arranged between the corresponding word and bit lines. Each of the memory cells includes a selection device layer, and a variable resistance layer, wherein the selection device layer includes a chalcogenide switching material having a composition according to a particular chemical formula.

公开(公告)号：US20190097129A1

公开(公告)日：2019-03-28

申请号：US16185161

申请日：2018-11-09

申请人： Micron Technology, Inc.

发明人： Jun Liu ,  Kunal Parekh

IPC分类号： H01L45/00 ,  H01L27/24

CPC分类号： H01L45/06 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1683 ,  H01L45/1691

摘要： In some embodiments, an integrated circuit includes narrow, vertically-extending pillars that fill openings formed in the integrated circuit. In some embodiments, the openings can contain phase change material to form a phase change memory cell. The openings occupied by the pillars can be defined using crossing lines of sacrificial material, e.g., spacers, that are formed on different vertical levels. The lines of material can be formed by deposition processes that allow the formation of very thin lines. Exposed material at the intersection of the lines is selectively removed to form the openings, which have dimensions determined by the widths of the lines. The openings can be filled, for example, with phase change material.

公开(公告)号：US20190081103A1

公开(公告)日：2019-03-14

申请号：US16184465

申请日：2018-11-08

申请人： Micron Technology, Inc.

发明人： Paolo Fantini ,  F. Daniel Gealy ,  Enrico Varesi ,  Swapnil A. Lengade

IPC分类号： H01L27/24 ,  C01B19/00 ,  C01B35/14 ,  H01L27/11514 ,  H01L27/11507 ,  H01L45/00

CPC分类号： H01L27/2427 ,  C01B19/007 ,  C01B35/14 ,  G11C11/22 ,  G11C13/0004 ,  G11C2213/71 ,  G11C2213/73 ,  H01L27/11507 ,  H01L27/11514 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143

摘要： Systems, devices, and methods related to or that employ chalcogenide memory components and compositions are described. A memory device, such as a selector device, may be made of a chalcogenide material composition. A chalcogenide material may have a composition that includes one or more elements from the boron group, such as boron, aluminum, gallium, indium, or thallium. A selector device, for instance, may have a composition of selenium, arsenic, and at least one of boron, aluminum, gallium, indium, or thallium. The selector device may also be composed of germanium or silicon, or both. The relative amount of boron, aluminum, gallium, indium, or thallium may affect a threshold voltage of a memory component, and the relative amount may be selected accordingly. A memory component may, for instance have a composition that includes selenium, arsenic, and some combination of germanium, silicon, and at least one of boron, aluminum, gallium, indium, or thallium.

公开(公告)号：US20180358410A1

公开(公告)日：2018-12-13

申请号：US15986932

申请日：2018-05-23

申请人： SK hynix Inc.

发明人： Sanghun LEE

IPC分类号： H01L27/24 ,  H01L45/00

CPC分类号： H01L27/2463 ,  G11C11/22 ,  G11C13/0007 ,  G11C13/0069 ,  H01L45/06 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

摘要： A resistance change memory device includes a lower electrode, a ferroelectric material layer disposed on the lower electrode, a resistance switching material layer disposed on the ferroelectric material layer, and an upper electrode disposed on the resistance switching material layer.

公开(公告)号：US20180315796A1

公开(公告)日：2018-11-01

申请号：US15828014

申请日：2017-11-30

申请人： SK hynix Inc.

发明人： Jong Chul LEE ,  Jongho LEE

IPC分类号： H01L27/24 ,  H01L23/528 ,  H01L45/00 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L27/22 ,  H01L43/10

CPC分类号： H01L27/2463 ,  H01L23/528 ,  H01L27/224 ,  H01L27/2409 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1608 ,  H01L45/165 ,  H01L45/1675

摘要： A method of manufacturing a cross-point memory array device is disclosed. In the method, a substrate is provided. A plurality of first conductive line patterns are formed over the substrate. An insulating layer is formed over the first conductive line patterns. The insulating layer includes an insulative oxide. A plurality of switching film patterns are formed on the first conductive line patterns by selectively doping a plurality regions of the insulating layer. A plurality of memory structures are formed on the plurality of switching film patterns, respectively. A plurality of second conductive line patterns are formed on the plurality of memory structures.

公开(公告)号：US20180277601A1

公开(公告)日：2018-09-27

申请号：US15832958

申请日：2017-12-06

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Dong-ho Ahn ,  Zhe Wu ,  Soon-oh Park ,  Hideki Horii

IPC分类号： H01L27/24 ,  H01L45/00

CPC分类号： H01L27/2427 ,  H01L27/224 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/126 ,  H01L45/141 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/1683

摘要： A memory device is provided. The memory device includes a variable resistance layer. A selection device layer is electrically connected to the variable resistance layer. The selection device layer includes a chalcogenide switching material having a composition according to chemical formula 1 below, [GeASeBTeC](1-U)[X]U  (1) where 0.20≤A≤0.40, 0.40≤B≤0.70, 0.05≤C≤0.25, A+B+C=1, 0.0≤U≤0.20, and X is at least one selected from boron (B), carbon (C), nitrogen (N), oxygen (O), phosphorus (P), or sulfur (S).

公开(公告)号：US10084017B2

公开(公告)日：2018-09-25

申请号：US15109692

申请日：2015-01-07

申请人： SONY CORPORATION

发明人： Kazuhiro Ohba ,  Hiroaki Sei

IPC分类号： H01L47/00 ,  H01L27/24 ,  G11C13/00 ,  H01L45/00

CPC分类号： H01L27/2481 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0073 ,  G11C2213/73 ,  G11C2213/76 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1625 ,  H01L45/1641

摘要： A switch device includes: a first electrode; a second electrode disposed to oppose the first electrode; a switch layer provided between the first electrode and the second electrode, and including at least one or more kinds of chalcogen elements and one or more kinds of first elements out of the one or more kinds of chalcogen elements, the one or more kinds of first elements, and a second element including one or both of oxygen (O) and nitrogen (N), the one or more kinds of chalcogen elements being selected from tellurium (Te), selenium (Se), and sulfur (S), and the one or more kinds of first elements being selected from boron (B), carbon (C), and silicon (Si).

公开(公告)号：US09978937B2

公开(公告)日：2018-05-22

申请号：US15153868

申请日：2016-05-13

申请人： Micron Technology, Inc.

发明人： Eugene P. Marsh

IPC分类号： H01L45/00 ,  H01L21/02 ,  C23C16/34

CPC分类号： H01L45/06 ,  C23C16/345 ,  H01L21/0217 ,  H01L21/02208 ,  H01L21/02211 ,  H01L21/0228 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608

摘要： Some embodiments include methods utilizing atomic layer deposition to form material containing silicon and nitrogen (e.g., silicon nitride). The atomic layer deposition uses Sil4 as one precursor and uses a nitrogen-containing material as another precursor. Some embodiments include methods of forming a structure in which a chalcogenide region is formed over a semiconductor substrate; and in which Sil4 is used as a precursor during formation of silicon nitride material directly against a surface of the chalcogenide region.

公开(公告)号：US20180138242A1

公开(公告)日：2018-05-17

申请号：US15858811

申请日：2017-12-29

申请人： Micron Technology, Inc.

发明人： Samuele Sciarrillo

IPC分类号： H01L27/24 ,  H01L45/00

CPC分类号： H01L27/2481 ,  H01L27/2427 ,  H01L27/2445 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1675

摘要： The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a memory device of the memory array comprises a substrate and a memory cell stack formed between and electrically connected to first and second conductive lines. The memory cell stack comprises a first memory element over the substrate and a second memory element formed over the first element, wherein one of the first and second memory elements comprises a storage element and the other of the first and second memory elements comprises a selector element. The memory cell stack additionally comprises a first pair of sidewalls opposing each other and a second pair of sidewalls opposing each other and intersecting the first pair of sidewalls. The memory device additionally comprises first protective dielectric insulating materials formed on a lower portion of the first pair of sidewalls and an isolation dielectric formed on the first protective dielectric insulating material and further formed on an upper portion of the first pair of sidewalls.