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公开(公告)号：US11812619B2
公开(公告)日：2023-11-07
申请号：US17227852
申请日：2021-04-12
发明人： Jinwoo Lee , Zhe Wu , Dongsung Choi , Chungman Kim , Seunggeun Yu , Jabin Lee , Soyeon Choi
CPC分类号： H10B63/84 , H10N70/826 , H10N70/841
摘要： A resistive memory device includes a first conductive line extending in a first horizontal direction on a substrate, a plurality of second conductive lines separated from the first conductive line in a vertical direction and extending in a second horizontal direction intersecting with the first horizontal direction, on the substrate, a plurality of memory cells respectively connected between the first conductive line and one second conductive line selected from among the plurality of second conductive lines at a plurality of intersection points between the first conductive line and the plurality of second conductive lines, each of the plurality of memory cells including a selection device and a resistive memory pattern, and a bottom electrode shared by the plurality of memory cells, the bottom electrode having a variable thickness in the first horizontal direction, and including a top surface having a concave-convex shape.
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公开(公告)号：US11444127B2
公开(公告)日：2022-09-13
申请号：US17019649
申请日：2020-09-14
发明人： Jinwoo Lee , Kwangmin Park , Zhe Wu
摘要： A memory device including a first conductive line on a substrate and extending in a first horizontal direction; a second conductive line on the first conductive line and extending in a second horizontal direction that is perpendicular to the first horizontal direction; and a memory cell between the first conductive line and the second conductive line, the memory cell including a variable resistance memory layer, a buffer resistance layer, and a switch material pattern, extending in a vertical direction that is perpendicular to the first horizontal direction and the second horizontal direction, and having a tapered shape with a decreasing horizontal width along the vertical direction, wherein at least a part of the variable resistance memory layer and at least a part of the buffer resistance layer of the memory cell are at a same vertical level.
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公开(公告)号：US11211427B2
公开(公告)日：2021-12-28
申请号：US16386893
申请日：2019-04-17
发明人： Jinwoo Lee , Zhe Wu , Kyubong Jung , Seung-geun Yu , Ja Bin Lee
摘要： A switching element includes a lower barrier electrode disposed on a substrate, a switching pattern disposed on the lower barrier electrode, and an upper barrier electrode disposed on the switching pattern. The switching pattern includes a first switching pattern, and a second switching pattern disposed on the first switching pattern and having a density different from a density of the first switching pattern.
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公开(公告)号：US11152064B2
公开(公告)日：2021-10-19
申请号：US16530517
申请日：2019-08-02
发明人： Zhe Wu , Ja Bin Lee , Jin Woo Lee , Kyu Bong Jung
摘要： A memory device includes a word line, a bit line intersecting the word line, and a memory cell at an intersection of the word line and the bit line. The memory cell includes a first electrode connected to the word line; a second electrode connected to the bit line; and a selective element layer between the first electrode and the second electrode. The selective element layer includes one of Ge—Se—Te, Ge—Se—Te—As, and Ge—Se—Te—As—Si, and a composition ratio of arsenic (As) component of each of the Ge—Se—Te—As and the Ge—Se—Te—As—Si being greater than 0.01 and less than 0.17.
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公开(公告)号：US10388867B2
公开(公告)日：2019-08-20
申请号：US15294873
申请日：2016-10-17
发明人： Zhe Wu , Soon-Oh Park , Jeong-Hee Park , Dong-Ho Ahn , Hideki Horii
摘要： A variable resistance memory device including a selection pattern; an intermediate electrode contacting a first surface of the selection pattern; a variable resistance pattern on an opposite side of the intermediate electrode relative to the selection pattern; and a first electrode contacting a second surface of the selection pattern and including a n-type semiconductor material, the second surface of the selection pattern being opposite the first surface thereof.
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公开(公告)号：US10224371B2
公开(公告)日：2019-03-05
申请号：US15421498
申请日：2017-02-01
发明人： Zhe Wu , Dong-ho Ahn , Hideki Horii , Soon-oh Park , Jeong-hee Park , Jin-woo Lee , Dong-jun Seong , Seol Choi
摘要： A memory device includes a variable resistance layer and a selection device layer electrically connected to the variable resistance layer. The memory device further included a chalcogenide switching material that reduces leakage current and has, for example, a composition according to chemical formula 1 below, [GeXSiY(AsaTe1-a)Z](1-U)[N]U (1) (where 0.05≤X≤0.1, 0.15≤Y≤0.25, 0.7≤Z≤0.8, X+Y+Z=1, 0.45≤a≤0.6, and 0.08≤U≤0.2).
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7.发明申请PHYSICAL VAPOR DEPOSITION APPARATUS AND METHOD OF DEPOSITING PHASE-CHANGE MATERIALS USING THE SAME 审中-公开物理蒸气沉积装置及使用相变材料沉积相变材料的方法公开(公告)号：US20160102396A1
公开(公告)日：2016-04-14
申请号：US14876183
申请日：2015-10-06
发明人： Zhe Wu , Jung-Hwan Park , Jeong-Hee Park , Dong-Ho Ahn
CPC分类号： C23C14/541 , C23C14/0623 , C23C14/50 , C23C14/542 , C23C14/548 , H01J37/32522 , H01J37/32623 , H01J37/32724 , H01J37/34
摘要： A physical vapor deposition (PVD) apparatus for forming a phase-changeable layer includes a process chamber including a loading chamber configured to load a substrate, and a depositing chamber configured to deposit ion particles of a phase-changeable material onto the substrate; a target member on an upper portion of the depositing chamber and configured to provide the ion particles of the phase-changeable material which react with process gases in a plasma state; a plasma generator configured to generate a process gas plasma from the process gases; a chuck on a lower portion of the depositing chamber and holding the substrate, the chuck including a heater configured to heat the substrate, and at least one electrode configured to guide the ion particles of the phase-changeable material to the substrate; and a supplementary heater in the process chamber and configured to transfer radiant heat around the substrate.
摘要翻译： 用于形成相变层的物理气相沉积（PVD）装置包括处理室，该处理室包括被配置为加载基板的装载室和被配置成将相变材料的离子颗粒沉积到基板上的沉积室; 沉积室上部的目标构件，其构造成提供与等离子体状态的处理气体反应的相变材料的离子颗粒; 等离子体发生器，其被配置为从所述处理气体产生处理气体等离子体; 卡盘位于沉积室的下部并保持基板，卡盘包括构造成加热基板的加热器和至少一个电极，其被配置为将相变材料的离子颗粒引导到基板; 以及处理室中的附加加热器，并且被配置为在衬底周围传递辐射热。
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公开(公告)号：US11856794B2
公开(公告)日：2023-12-26
申请号：US17364378
申请日：2021-06-30
发明人： Dong Sung Choi , Jong Uk Kim , Kwang Min Park , Zhe Wu , Ja Bin Lee , Jae Ho Jung
CPC分类号： H10B63/24 , H10N70/841 , H10N70/8828
摘要： A semiconductor memory device includes a first memory cell provided on a substrate, a second memory cell provided on the substrate and spaced apart from the first memory cell, a passivation layer extending along a side surface of the first memory cell and a side surface of the second memory cell, and a gap fill layer covering the passivation layer. Each of the first memory cell and the second memory cell includes a selection pattern having ovonic threshold switching characteristics, and a storage pattern provided on the selection pattern. The passivation layer includes a lower portion filling a space between the selection pattern of the first memory cell and the selection pattern of the second memory cell, and an upper portion extending along a side surface of the storage pattern of each of the first memory cell and the second memory cell.
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公开(公告)号：US20220059615A1
公开(公告)日：2022-02-24
申请号：US17364378
申请日：2021-06-30
发明人： Dong Sung CHOI , Jong Uk Kim , Kwang Min Park , Zhe Wu , Ja Bin Lee , Jae Ho Jung
摘要： A semiconductor memory device includes a first memory cell provided on a substrate, a second memory cell provided on the substrate and spaced apart from the first memory cell, a passivation layer extending along a side surface of the first memory cell and a side surface of the second memory cell, and a gap fill layer covering the passivation layer. Each of the first memory cell and the second memory cell includes a selection pattern having ovonic threshold switching characteristics, and a storage pattern provided on the selection pattern. The passivation layer includes a lower portion filling a space between the selection pattern of the first memory cell and the selection pattern of the second memory cell, and an upper portion extending along a side surface of the storage pattern of each of the first memory cell and the second memory cell.
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公开(公告)号：US20200075675A1
公开(公告)日：2020-03-05
申请号：US16446812
申请日：2019-06-20
发明人： Zhe Wu , Ja-bin Lee , Jin-woo Lee , Kyu-bong Jung
摘要： A memory device includes first conductive lines extending in a first direction, second conductive lines extending in a second direction, and a plurality of memory cells each arranged between the first and second conductive lines and each including a variable resistance memory layer and a switch material pattern. The switch material pattern includes an element injection area arranged in an outer area of the switch material pattern, and an internal area covered by the element injection area. The internal area contains a first content of at least one element from arsenic (As), sulfur (S), selenium (Se), and tellurium (Te), the element injection area contains a second content of the at least one element from As, S, Se, and Te, and the second content has a profile in which a content of the at least one element decreases away from the at least one surface of the switch material pattern.
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