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公开(公告)号：US20240081155A1
公开(公告)日：2024-03-07
申请号：US17938967
申请日：2022-09-07
发明人： Young-suk Choi , Qinli Ma , Wei-Chuan Chen
CPC分类号： H01L43/02 , H01F10/3254 , H01L27/222 , H01L43/10
摘要： A semiconductor memory device includes a bottom electrode, a magnetic tunnel junction (MTJ) structure disposed over the bottom electrode, a seed layer disposed between the MTJ structure and the bottom electrode, and a non-magnetic amorphous insertion layer disposed between the seed layer and the bottom electrode.
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公开(公告)号：US20240032441A1
公开(公告)日：2024-01-25
申请号：US17892162
申请日：2022-08-22
发明人： Chih-Wei Kuo , Hung-Chan Lin , Chung Yi Chiu
CPC分类号： H01L43/04 , H01L27/222 , H01L43/06 , H01L43/10 , H01L43/14
摘要： Provided is a magnetoresistive random access memory (MRAM) device including a bottom electrode, a magnetic tunnel junction (MTJ) structure, a first spin orbit torque (SOT) layer, a cap layer, a second SOT layer, an etch stop layer, and an upper metal line layer. The MTJ structure is disposed on the bottom electrode. The first SOT layer is disposed on the MTJ structure. The cap layer is disposed on the first SOT layer. The second SOT layer is disposed on the cap layer. The etch stop layer is disposed on the second SOT layer. The upper metal line layer penetrates though the etch stop layer and is landed on the second SOT layer.
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公开(公告)号：US20240027547A1
公开(公告)日：2024-01-25
申请号：US17813412
申请日：2022-07-19
发明人： Samridh Jaiswal , Paolo Campiglio
CPC分类号： G01R33/093 , H01F10/3286 , H01L43/10 , H01L43/08 , G01R33/098
摘要： Methods and apparatus for a magnetoresistive (MR) sensor a free layer with a thickness of the CoFeB material to produce out-of-plane sensing for the sensor and a reference layer magnetically coupled to the free layer. A dusting layer of an oxide material is disposed on the free layer to achieve perpendicular magnetic anisotropy for an interface of the oxide layer and the free layer for a desired sensitivity for the sensor.
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公开(公告)号：US20240023458A1
公开(公告)日：2024-01-18
申请号：US17887042
申请日：2022-08-12
发明人： Dmytro Apalkov , Jaewoo Jeong , Ikhtiar
CPC分类号： H01L43/08 , H01L43/02 , H01L43/10 , H01L43/12 , H01L27/222
摘要： A spin-orbit torque magnetic random-access memory (SOT-MRAM) device includes a substrate, a spin orbit torque line above the substrate, a composite-metal-oxide seed layer above the spin orbit torque line, and a magnetic tunnel junction above the composite-metal-oxide seed layer. The magnetic tunnel junction includes a free layer above the composite-metal-oxide seed layer, a main tunneling barrier layer above the free layer, and a pinned layer above the main tunneling barrier layer.
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公开(公告)号：US20240008369A1
公开(公告)日：2024-01-04
申请号：US17878082
申请日：2022-08-01
发明人： Hui-Lin Wang
CPC分类号： H01L43/08 , H01L27/228 , H01L43/02 , H01L43/10
摘要： A semiconductor device includes a bottom electrode on a substrate, a magnetic tunneling junction (MTJ) on the bottom electrode, a first cap layer on the MTJ, a second cap layer on the first cap layer, a block layer on the second cap layer, and a top electrode on the block layer. Preferably, the block layer could be made of Co-based alloy or metal nitride, in which the Co-based alloy could further include CoW alloy whereas the metal nitride could include WN.
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6.发明公开公开(公告)号：US20230413681A1
公开(公告)日：2023-12-21
申请号：US17807485
申请日：2022-06-17
发明人： Panagiotis Charilaos Filippou , Chirag Garg , See-Hun Yang , Mahesh Samant , . Ikhtiar , Jaewoo Jeong
CPC分类号： H01L43/02 , H01L27/222 , H01L43/10 , H01L43/12
摘要： A magnetic random access memory (MRAM) stack, a method of fabricating a MRAM stack, a MRAM array, and a computer system. The MRAM stack includes a first magnetic layer comprising a Heusler compound. The MRAM stack also includes one or more seed layers including a templating structure having a crystalline structure configured to template the Heusler compound. The magnetic layer is formed over the templating structure. The MRAM stack also includes a chromium (Cr) layer formed under the templating structure. The Cr layer is configured to enhance a tunnel magnetoresistance (TMR) of the MRAM stack.
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公开(公告)号：US11849645B2
公开(公告)日：2023-12-19
申请号：US17833688
申请日：2022-06-06
发明人： Wei-Hao Liao , Hsi-Wen Tien , Chih-Wei Lu , Pin-Ren Dai , Chung-Ju Lee
摘要： An integrated circuit includes a substrate, a bottom electrode, a dielectric layer, a metal-containing compound layer, a resistance switching element, and a top electrode. The bottom electrode is over the substrate, the bottom electrode having a bottom portion and a top portion over the bottom portion. The bottom portion of the bottom electrode has a sidewall slanted with respect to a sidewall of the top portion of the bottom electrode. The dielectric layer surrounds the bottom portion of the bottom electrode. The metal-containing compound layer surrounds the top portion of the bottom electrode. A top end of the sidewall of the bottom portion of the bottom electrode is higher than a bottom surface of the metal-containing compound layer. The resistance switching element is over the bottom electrode. The top electrode is over the resistance switching element.
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公开(公告)号：US20230389434A1
公开(公告)日：2023-11-30
申请号：US17804795
申请日：2022-05-31
CPC分类号： H01L43/12 , H01L43/02 , H01L43/10 , H01L43/08 , G11C11/161 , H01L27/222
摘要： A memory device includes a magnetic tunnel junction pillar above a bottom electrode. A sidewall spacer is disposed along sidewalls of the magnetic tunnel junction pillar with an uppermost surface of the sidewall spacer being coplanar with an uppermost surface of the magnetic tunnel junction pillar. A dielectric hardmask composed of an amorphous dielectric material is disposed above a first portion of the uppermost surface of the magnetic tunnel junction pillar, the dielectric hardmask includes a hemispherical shape. A top electrode is located surrounding the dielectric hardmask and above the uppermost surface of the sidewall spacer and a second portion of the uppermost surface of the magnetic tunnel junction pillar extending outwards from the dielectric hardmask.
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公开(公告)号：US20230371275A1
公开(公告)日：2023-11-16
申请号：US17880186
申请日：2022-08-03
发明人： Yu-Jen Wang , Sheng-Huang Huang , Harry-Hak-Lay Chuang , Hung Cho Wang , Ching-Huang Wang , Kuo-Feng Huang
CPC分类号： H01L27/222 , H01L43/02 , H01L43/10 , H01L43/12
摘要： A semiconductor device according to the present disclosure includes a first conductive feature and a second conductive feature in a first dielectric layer, a buffer layer over the first dielectric layer, a second dielectric layer over the buffer layer, a first bottom via extending through the buffer layer and the second dielectric layer, a second bottom via extending through the buffer layer and the second dielectric layer, a first bottom electrode disposed on the first bottom via, a second bottom electrode disposed on the second bottom via, a first magnetic tunnel junction (MTJ) stack over the first bottom electrode, and a second MTJ stack over the second bottom electrode. The first MTJ stack and the second MTJ stack have a same thickness. The first MTJ stack has a first width and the second MTJ stack has a second width greater than the first width.
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公开(公告)号：US20230320230A1
公开(公告)日：2023-10-05
申请号：US17709074
申请日：2022-03-30
申请人： Intel Corporation
发明人： Punyashloka Debashis , Hai Li , Chia-Ching Lin , Dmitri Evgenievich Nikonov , Ian Alexander Young
CPC分类号： H01L43/10 , H01L43/04 , H01L43/065 , H01L43/14 , H01L27/228 , H03K19/18
摘要： In one embodiment, an integrated circuit die includes: a first layer comprising a magnetoelectric material; a second layer comprising a monolayer transition metal dichalcogenide (TMD); a magnet between the first layer and the second layer, wherein the magnet has perpendicular magnetic anisotropy; a first conductive trace coupled to the first layer; and a second conductive trace coupled to the magnet.
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