公开(公告)号：US20240243748A1

公开(公告)日：2024-07-18

申请号：US18416395

申请日：2024-01-18

Applicant: Board of Regents, The University of Texas System

Inventor： Joseph S. Friedman ,  Benjamin W. Walker ,  Xuan Hu ,  Alexander J. Edwards

IPC: H03K19/20 ,  H01F10/32 ,  H03K19/18 ,  H10N52/80

CPC classification number: H03K19/20 ,  H01F10/3286 ,  H03K19/18 ,  H10N52/80

Abstract: A method for skyrmion based processing is provided. The method comprises generating a number of skyrmions. The skyrmions are moved down a skyrmion racetrack using a multi-phase voltage-controlled magnetic anisotropy (VCMA) clock. A number of logical operations are performed with zero or more skyrmions belonging to the same clock cycle that meet at a logical junction. Outputs of the logical operations fan out to other logic gates for computation of any arbitrary combinatorial function.

公开(公告)号：US20190189175A1

公开(公告)日：2019-06-20

申请号：US16285948

申请日：2019-02-26

Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Byong Guk Park ,  Seung Heon Baek ,  Kyung Woong Park

IPC: G11C11/16 ,  G11C11/56 ,  G11C11/18 ,  H03K19/18 ,  H01L43/08 ,  H01L43/06 ,  H01L27/22

CPC classification number: G11C11/1675 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1697 ,  G11C11/18 ,  G11C11/5607 ,  H01L27/228 ,  H01L43/06 ,  H01L43/08 ,  H03K19/18 ,  H03K19/20

Abstract: The present invention relates to a semiconductor device. The semiconductor device based on the spin orbit torque (SOT) effect, according to an example of the present invention, comprises the first electrode; and the first cell and the second cell connected to the first electrode, wherein the first and the second cells are arranged on the first electrode separately; the magnetic tunnel junction (MTJ) having a free magnetic layer and a pinned magnetic layer with a dielectric layer in between them; the magnetization direction of the free magnetic layer is changed when the current applied on the first electrode exceeds critical current value of each cell; and the critical current value of the first cell is different from that of the second cell.

公开(公告)号：US20190189173A1

公开(公告)日：2019-06-20

申请号：US16326308

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Sasikanth MANIPATRUNI ,  Ian YOUNG ,  Dmitri NIKONOV

IPC: G11C11/16 ,  H03K19/16 ,  H01L29/66 ,  H01L29/82 ,  H03K19/18

CPC classification number: G11C11/161 ,  H01L29/66984 ,  H01L29/82 ,  H01L43/06 ,  H03K19/16 ,  H03K19/18

Abstract: Methods and apparatus for complex number generation and operation on a chip are disclosed. A disclosed logic device includes a first magnet with a first preferred direction of magnetization to polarize a spin of electrons in the first direction. The example logic device includes a second magnet with a second preferred direction of magnetization that polarizes a spin of electrons in the second direction. The example logic device includes a third magnet providing a free layer without a preferred direction of magnetization that is connected to the first and second magnets, wherein the third magnet encodes a vector based on a flux of electrons spin polarized in the first direction and a flux of electrons spin polarized in the second direction.

公开(公告)号：US20180350432A1

公开(公告)日：2018-12-06

申请号：US16060042

申请日：2017-04-14

Applicant: TDK CORPORATION

Inventor： Tomoyuki SASAKI

IPC: G11C11/56 ,  H01L43/02 ,  G11C11/16 ,  H01L27/22 ,  H01F10/32 ,  H03K19/18 ,  G11C11/54

CPC classification number: G11C11/5607 ,  G06N3/0635 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/54 ,  G11C27/00 ,  G11C2211/5615 ,  H01F10/3254 ,  H01F10/3272 ,  H01F10/3286 ,  H01F10/329 ,  H01L27/222 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H03K19/18

Abstract: A magnetic wall utilization-analog memory element includes a magnetic wall driving layer including a magnetic wall, a first region, a second region, and a third region located between the first region and the second region, a magnetization fixed layer provided at a the third region through a nonmagnetic layer, and a lower electrode layer provided at a position in the third region that overlaps the magnetization fixed layer in plan view on a second surface opposite to a first surface on which the magnetization fixed layer is provided.

公开(公告)号：US20170294577A1

公开(公告)日：2017-10-12

申请号：US15630034

申请日：2017-06-22

Applicant: SII Semiconductor Corporation

Inventor： Takaaki HIOKA ,  Mika EBIHARA

IPC: H01L43/14 ,  H01L43/04 ,  G01R33/07 ,  H01L43/06

CPC classification number: H01L43/14 ,  G01D5/145 ,  G01R15/202 ,  G01R15/207 ,  G01R21/08 ,  G01R33/0005 ,  G01R33/0052 ,  G01R33/0206 ,  G01R33/07 ,  G01R33/072 ,  G01R33/077 ,  H01L23/13 ,  H01L23/145 ,  H01L23/15 ,  H01L23/32 ,  H01L43/04 ,  H01L43/065 ,  H02K11/215 ,  H03K17/9517 ,  H03K19/18 ,  H04Q2213/307

Abstract: Provided are a magnetic sensor and a method of manufacturing the same. In the magnetic sensor and the method of manufacturing the same, a magnetic converging plate holder with a recessed pattern having the same shape and size as those of a magnetic converging plate is formed in a die pad of a package on which a semiconductor substrate having Hall elements, a circuit, and the like is to be arranged, the magnetic converging plate manufactured through processes different from those of the semiconductor substrate on which the Hall elements and the circuit are formed is inserted into the magnetic converging plate holder, and the semiconductor substrate having the Hall elements, the circuit, and the like is arranged on the resultant so that a back surface thereof faces the die pad and the magnetic converging plate.

公开(公告)号：US09711200B2

公开(公告)日：2017-07-18

申请号：US15054401

申请日：2016-02-26

Applicant: Northwestern University

Inventor： Joseph Shimon Friedman ,  Alan V. Sahakian

IPC: G11C11/16 ,  H01L43/02 ,  H01L29/82 ,  H01L27/22 ,  H01L43/08 ,  H03K19/18

CPC classification number: G11C11/161 ,  G11C11/1675 ,  H01L27/22 ,  H01L29/82 ,  H01L43/02 ,  H01L43/08 ,  H03K19/18

Abstract: A magnetic tunnel junction (MTJ) device is provided that includes a MTJ element and a control wire. The MTJ element includes a top ferromagnet layer formed of a first magnetic material, a tunneling layer, and a bottom ferromagnet layer formed of a second magnetic material. The tunneling layer is mounted between the top ferromagnet layer and the bottom ferromagnet layer. The control wire is configured to conduct a charge pulse. A direction of charge flow in the control wire extends substantially perpendicular to a magnetization direction of the top ferromagnet layer. The control wire is positioned sufficiently close to the top ferromagnet layer to reverse the magnetization direction of the top ferromagnet layer when the charge pulse flows therethrough while not reversing the magnetization direction of the bottom ferromagnet layer when the charge pulse flows therethrough.

公开(公告)号：US20170179373A1

公开(公告)日：2017-06-22

申请号：US15387350

申请日：2016-12-21

Applicant: IMEC VZW

Inventor： Johan Swerts ,  Mauricio MANFRINI ,  Christoph ADELMANN

IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22

CPC classification number: H01L43/02 ,  H01L27/22 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H03K19/18 ,  H03K19/23

Abstract: The disclosed technology relates generally to magnetic devices, and more particularly to spin torque majority gate devices such as spin torque magnetic devices (STMG), and to methods of fabricating the same. In one aspect, a majority gate device includes a plurality of input zones and an output zone. A magnetic tunneling junction (MTJ) is formed in each of the input zones and the output zone, where the MTJ includes a non-magnetic layer interposed between a free layer stack and a hard layer. The free layer stack in turn includes a bulk perpendicular magnetic anisotropy (PMA) layer on a seed layer, a magnetic layer formed on and in contact with the bulk PMA layer, and a non-magnetic layer formed on the magnetic layer. Each of the bulk PMA layer and the seed layer is configured as a common layer for each of the input zones and the output zone.

公开(公告)号：US20170178711A1

公开(公告)日：2017-06-22

申请号：US14975439

申请日：2015-12-18

Applicant: Intel Corporation

Inventor： Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young

IPC: G11C11/22

CPC classification number: G11C11/223 ,  G11C11/221 ,  G11C11/2297 ,  H03K19/0016 ,  H03K19/18

Abstract: Described is an apparatus which comprises: a first power domain having a first inverter to be powered by a first switchable positive supply and a first switchable negative supply; and a second power domain having a second inverter including p-type and n-type FE-FETs, the second inverter having an input coupled to an output of the first inverter.

公开(公告)号：US20170076774A1

公开(公告)日：2017-03-16

申请号：US14974282

申请日：2015-12-18

Applicant: Keisuke NAKATSUKA

Inventor： Keisuke NAKATSUKA

IPC: G11C11/16 ,  H03K19/18 ,  H01L43/08 ,  G11C5/06 ,  H01L27/22

CPC classification number: G11C11/1675 ,  G11C5/063 ,  H01L27/222 ,  H01L43/08 ,  H03K19/18

Abstract: According to one embodiment, a logical operation circuit includes a magnetic tunnel junction (MTJ) element and driver. The MTJ element includes a first magnetic layer, a second magnetic layer, and an intermediate layer between the first and second magnetic layers. An orientation of magnetization of the second magnetic layer flips by a first current which flows through the MTJ element in a first state from the second magnetic layer to the first magnetic layer. The driver is coupled to the first magnetic layer without a magnetic layer interposed and coupled to the second magnetic layer, and passes a second current through the MTJ element in the first state from the second magnetic layer to the first magnetic layer. A magnitude of the second current is larger than 1.5 times a magnitude of the first current.

Abstract translation: 根据一个实施例，逻辑运算电路包括磁隧道结（MTJ）元件和驱动器。 MTJ元件包括第一磁性层，第二磁性层和第一和第二磁性层之间的中间层。 第二磁性层的磁化取向由第一状态从第二磁性层流过第一磁性层的MTJ元件的第一电流翻转。 驱动器耦合到第一磁性层，而没有插入并耦合到第二磁性层的磁性层，并且使第二电流通过第一状态的MTJ元件从第二磁性层传递到第一磁性层。 第二电流的大小大于第一电流的1.5倍。

公开(公告)号：US09543955B2

公开(公告)日：2017-01-10

申请号：US14849621

申请日：2015-09-10

Applicant: Huazhong University of Science and Technology

Inventor： Xiangshui Miao ,  Yi Li ,  Yingpeng Zhong

IPC: H03K19/08 ,  G11C11/16 ,  G11C13/00 ,  H03K19/177 ,  G11B5/02 ,  H03K19/18

CPC classification number: H03K19/08 ,  G11B5/02 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0097 ,  H03K19/1776 ,  H03K19/18

Abstract: A non-volatile logic device, including: a substrate, a magnetic head, a base electrode, an insulating layer, a phase-change magnetic film, and a top electrode. The substrate includes a silicon substrate and an active layer attached to the silicon substrate. The base electrode includes an N-type silicon layer, a P-type silicon layer and a heating layer, the N-type silicon layer and the P-type silicon layer constitute a PN diode structure, and the size of the heating layer is smaller than that of the P-type silicon layer. The phase-change magnetic film is deposited on the insulating layer and is electrically contacted with the heating layer. The top electrode and the base electrode are connected to an external electrical pulse signal, and an external magnetic field parallel to a two dimensional plane of the phase-change magnetic film is applied to the non-volatile logic device.

Abstract translation: 一种非易失性逻辑器件，包括：基板，磁头，基极，绝缘层，相变磁性膜和顶部电极。 衬底包括硅衬底和附着到硅衬底的有源层。 基极包括N型硅层，P型硅层和加热层，N型硅层和P型硅层构成PN二极管结构，加热层的尺寸较小 比P型硅层高。 相变磁性膜沉积在绝缘层上并与加热层电接触。 顶部电极和基极连接到外部电脉冲信号，并且将平行于相变磁性膜的二维平面的外部磁场施加到非易失性逻辑器件。