公开(公告)号：US20230320230A1

公开(公告)日：2023-10-05

申请号：US17709074

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Punyashloka Debashis ,  Hai Li ,  Chia-Ching Lin ,  Dmitri Evgenievich Nikonov ,  Ian Alexander Young

IPC: H01L43/10 ,  H01L43/04 ,  H01L43/06 ,  H01L43/14 ,  H01L27/22

CPC classification number: H01L43/10 ,  H01L43/04 ,  H01L43/065 ,  H01L43/14 ,  H01L27/228 ,  H03K19/18

Abstract: In one embodiment, an integrated circuit die includes: a first layer comprising a magnetoelectric material; a second layer comprising a monolayer transition metal dichalcogenide (TMD); a magnet between the first layer and the second layer, wherein the magnet has perpendicular magnetic anisotropy; a first conductive trace coupled to the first layer; and a second conductive trace coupled to the magnet.

公开(公告)号：US20230165162A1

公开(公告)日：2023-05-25

申请号：US18058426

申请日：2022-11-23

Applicant: Melexis Technologies SA

Inventor： Brecht PUT ,  Tim VANGERVEN

IPC: H01L43/06 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L43/065 ,  H01L23/562 ,  H01L23/3107

Abstract: An integrated sensor and method for manufacturing the sensor includes a first component having a first material with a predetermined first value of coefficient of thermal expansion (CTE), and a second component over the first component. The second component includes a second material with a predetermined second value of CTE different from the first value. An interlayer is provided by molecular layer deposition, for minimizing stress caused by coefficient of thermal expansion mismatch between the first and second components. The interlayer includes an organic-inorganic hybrid polymer compound.

公开(公告)号：US20190036011A1

公开(公告)日：2019-01-31

申请号：US15661826

申请日：2017-07-27

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Bin LIU ,  Eng Huat TOH ,  Ruchil Kumar JAIN

IPC: H01L43/04 ,  H01L43/06 ,  H01L43/14 ,  G01R33/07 ,  G01R33/02 ,  G01R33/00

CPC classification number: H01L43/04 ,  G01R33/0052 ,  G01R33/0206 ,  G01R33/077 ,  H01L27/22 ,  H01L43/065 ,  H01L43/14

Abstract: A method of forming a 3D Hall effect sensor and the resulting device are provided. Embodiments include forming a p-type well in a substrate; forming a first n-type well in a first region surrounded by the p-type well in top view; forming a second n-type well in a second region surrounding the p-type well; providing n-type dopant in the first and second n-type wells; and providing p-type dopant in the p-type well and the first n-type well.

公开(公告)号：US20180350498A1

公开(公告)日：2018-12-06

申请号：US15572017

申请日：2016-04-18

Applicant: Mohammad Kazemi ,  Engin Ipek ,  Eby G. Friedman

Inventor： Mohammad Kazemi ,  Engin Ipek ,  Eby G. Friedman

IPC: H01F10/32 ,  G11C11/16 ,  H01L43/10 ,  H03K19/18 ,  G11C11/18 ,  H01L43/06

CPC classification number: H01F10/3286 ,  G11C11/161 ,  G11C11/1675 ,  G11C11/18 ,  H01F10/329 ,  H01L43/00 ,  H01L43/065 ,  H01L43/10 ,  H03K19/18

Abstract: A base element for switching a magnetization state of a nanomagnet includes a heavy-metal strip having a surface. A ferromagnetic nanomagnet is disposed adjacent to the surface. The ferromagnetic nanomagnet has a first magnetization equilibrium state and a second magnetization equilibrium state. The first magnetization equilibrium state or the second magnetization equilibrium state is settable in an absence of an external magnetic field by a flow of electrical charge through the heavy-metal strip. A method for switching a magnetization state of a nanomagnet is also described.

公开(公告)号：US10060991B2

公开(公告)日：2018-08-28

申请号：US15814986

申请日：2017-11-16

Applicant: SII Semiconductor Corporation

Inventor： Takaaki Hioka ,  Mika Ebihara

IPC: G01R33/07 ,  H01L43/04 ,  H01L43/06

CPC classification number: G01R33/077 ,  H01L43/04 ,  H01L43/065

Abstract: Provided is a semiconductor device including a vertical Hall element with improved sensitivity. The vertical Hall element includes: a semiconductor layer of a second conductivity type formed on the semiconductor substrate; a plurality of electrodes aligned along a straight line on a surface of the semiconductor layer and being impurity regions of the second conductivity type being higher in concentration than the semiconductor layer; a plurality of electrode isolation diffusion layers of the first conductivity type respectively arranged between adjacent electrodes of the plurality of electrodes on the surface of the semiconductor layer to isolate the plurality of electrodes from one another; and embedded layers being an impurity region of the second conductivity type which is higher in concentration than the semiconductor layer and being respectively provided substantially right below one of the plurality of electrode isolation diffusion layers between the semiconductor substrate and the semiconductor layer.

公开(公告)号：US10008248B2

公开(公告)日：2018-06-26

申请号：US15327017

申请日：2015-07-17

Applicant: Cornell University

Inventor： Robert A Buhrman ,  Minh-hai Nguyen ,  Chi-feng Pai ,  Daniel C Ralph

IPC: G11C11/16 ,  H01L43/04 ,  H01L43/06 ,  H01L43/08 ,  H01L43/10 ,  H01L27/22

CPC classification number: G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1697 ,  G11C11/18 ,  H01L27/222 ,  H01L29/66984 ,  H01L43/04 ,  H01L43/065 ,  H01L43/08 ,  H01L43/10

Abstract: Devices or circuits based on spin torque transfer (STT) and Spin Hall effect are disclosed by using a spin Hall effect (SHE) metal layer coupled to a magnetic free layer for various applications. The efficiency or strength of the STT effect based on this combination of SHE and STT can be enhanced by an interface modification between the SHE metal layer and the magnetic free layer or by modifying or engineering the SHE metal layer by doping the SHE metal with certain impurities or other means.

公开(公告)号：US10003013B2

公开(公告)日：2018-06-19

申请号：US14471678

申请日：2014-08-28

Applicant: Magnachip Semiconductor, Ltd.

Inventor： Francois Hebert ,  Seong Woo Lee ,  Jong Yeul Jeong ,  Hee Baeg An ,  Kang Sup Shin ,  Seong Min Choe ,  Young Joon Kim

IPC: G01R33/07 ,  H01L43/06

CPC classification number: H01L43/065 ,  G01R33/072

Abstract: A semiconductor device including a circuitry, a magnetic sensor, and a buried oxide. The circuitry is formed on a substrate. The magnetic sensor has a sensing area formed under the circuitry. The buried oxide is disposed between the circuitry and the magnetic sensor. The sensing are comprises an N-doped area and a P-doped area doped deeper than the N-doped area, and sensor contacts connect the sensing area with the circuitry through the buried oxide.

公开(公告)号：US20180076106A1

公开(公告)日：2018-03-15

申请号：US15686930

申请日：2017-08-25

Applicant: ROHM CO., LTD.

Inventor： Isamu NISHIMURA

IPC: H01L23/13 ,  H01L23/00 ,  H01L23/14 ,  H01L23/373 ,  H01L21/48 ,  H01L23/498 ,  H01L43/06 ,  H01L43/04

CPC classification number: H01L23/13 ,  H01L21/4803 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/145 ,  H01L23/24 ,  H01L23/31 ,  H01L23/3733 ,  H01L23/49827 ,  H01L23/5384 ,  H01L24/16 ,  H01L43/04 ,  H01L43/065 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/19042 ,  H01L2924/19101

Abstract: The present invention provides a semiconductor device and a method of making the same for suppressing warpages of an article due to a difference of temperature strains during the process of making the semiconductor device. The semiconductor device of the present invention includes a semiconductor element 31; a substrate 1 having a main surface 11 and formed with a recess 14 recessed from the main surface 11 and accommodating the semiconductor element 31; a wiring portion 20 connected to the substrate 1 and electrically connected to the semiconductor element 31; and a sealing resin 4 filled in the recess 14. The substrate 1 includes an electrical insulative synthetic resin. The recess 14 has a bottom surface 141 and a connecting surface 142 connected to the bottom surface141 and the main surface11. The connecting surface 142 includes a first inclined surface 142a having one end connected to the bottom surface 141 and inclined with respect to the bottom surface 141; a second inclined surface 142b having one end connected to the main surface 11 and inclined with respect to the main surface 11; and an intermediate surface 142c connected to another end of the first inclined surface 142a and another end of the second inclined surface 142b.

公开(公告)号：US09864020B2

公开(公告)日：2018-01-09

申请号：US14594499

申请日：2015-01-12

Applicant: Magnachip Semiconductor, Ltd.

Inventor： Francois Hebert

IPC: G01R33/07 ,  H01L43/14 ,  G01R33/00 ,  H01L43/06

CPC classification number: G01R33/077 ,  G01R33/0052 ,  H01L43/065 ,  H01L43/14

Abstract: A vertical Hall sensor, a Hall sensor module, and a method for manufacturing the same are provided. By applying a trench structure inside a substrate with respect to a ground terminal, a directional component parallel to surface of the substrate is maximized with respect to a current flow to detect the magnetic field with improved sensitivity.

公开(公告)号：US09825218B2

公开(公告)日：2017-11-21

申请号：US14881372

申请日：2015-10-13

Applicant: Board of Regents, The University of Texas System

Inventor： Allan MacDonald ,  Leonard Franklin Register, II ,  Emanuel Tutuc ,  Inti Sodemann ,  Hua Chen ,  Xuehao Mou ,  Sanjay K. Banerjee

IPC: H01L43/00 ,  H01L43/06 ,  H01L43/04 ,  H01L43/10

CPC classification number: H01L43/065 ,  G11C11/161 ,  H01L43/04 ,  H01L43/08 ,  H01L43/10 ,  H03K19/18

Abstract: A device or class of devices that provides a mechanism for controlling charge current flow in transistors that employs collective magnetic effects to overcome voltage limitations associated with single-particle thermionic emission as in conventional MOSFETs. Such a device may include two or more magnetic stacks with an easy-in-plane ferromagnetic film sandwiched between oppositely magnetically oriented perpendicular magnetization anisotropy (PMA) ferromagnets. Each stack includes two non-magnetic layers separating the easy-plane ferromagnetic film from the PMA layers. Charge current flow through one of these stacks controls the current-voltage negative differential resistance characteristics of the second stack through collective magnetic interactions. This can be exploited in a variety of digital logic gates consuming less energy than conventional CMOS integrated circuits. Furthermore, the easy-in-plane magnetic films may be subdivided into regions coupled through exchange interactions and the in-plane fixed magnetic layers in the input magnetic stacks can be used in non-volatile logic and memory.