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公开(公告)号：US20240206345A1
公开(公告)日：2024-06-20
申请号：US18065651
申请日：2022-12-14
CPC分类号： H01L43/02 , H01L27/222 , H01L43/12
摘要： A magnetic tunnel junction (MTJ) stack, and a metallic encapsulation layer surrounding vertical side surfaces of the MTJ stack, electrically and physically connected to a top electrode of the MTJ stack. A magnetic tunnel junction (MTJ) stack, and a metallic encapsulation layer surrounding vertical side surfaces of the MTJ stack, electrically and physically connected to a top electrode of the MTJ stack, where a lower horizontal surface of the metallic encapsulation layer is below a bottom electrode contact of the MTJ stack. Forming a magnetic tunnel junction (MTJ) stack and forming a metallic encapsulation layer surrounding vertical side surfaces of the MTJ stack, electrically and physically connected to a top electrode of the MTJ stack.
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2.发明公开公开(公告)号：US20240196755A1
公开(公告)日：2024-06-13
申请号：US18064261
申请日：2022-12-10
CPC分类号： H01L43/12 , G11C11/161 , H01F10/3272 , H01L27/222 , H01L43/02 , H01L43/08 , H01L43/10
摘要： A semiconductor device that includes a substrate, a crystalline bottom electrode layer on an upper side of the semiconductor substrate, a conductive crystalline metal layer above the crystalline bottom electrode layer, and a conductive oxide layer above the conductive crystalline metal layer. The conductive oxide layer has a low resistance. The semiconductor device also includes a magnetic tunnel junction (MTJ) above the conductive crystalline metal layer, the MTJ including a tunnel barrier layer, a free layer on a first side of the tunnel barrier layer and a reference layer on a second side of the tunnel barrier layer opposite the first side.
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公开(公告)号：US20240188446A1
公开(公告)日：2024-06-06
申请号：US18061491
申请日：2022-12-05
CPC分类号： H01L43/12 , G11C11/161 , G11C11/1657 , H01L23/5226 , H01L27/222 , H01L43/02 , H01L43/08
摘要： A semiconductor device including a magnetic tunnel junction (MTJ) stack and an upper word line of the MTJ stack surrounding vertical side surfaces of the MTJ stack. A semiconductor device including a magnetic tunnel junction (MTJ) stack and an upper word line for the MTJ stack surrounding vertical side surfaces and an upper surface of a reference layer of the MTJ stack. A method including forming a forming a magnetic tunnel junction (MTJ) stack and forming a dielectric encapsulation layer surrounding vertical side surfaces of a top electrode, a free layer, a tunneling barrier, a reference layer and a bottom electrode of the MTJ stack.
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公开(公告)号：US20240147869A1
公开(公告)日：2024-05-02
申请号：US17974148
申请日：2022-10-26
申请人： Harry Joseph TRODAHL , William Freeman HOLMES-HEWETT , Jackson David MILLER , Catherine Margaret Walker POT , Benjamin John RUCK , Eva-Maria Johanna ANTON
发明人： Harry Joseph TRODAHL , William Freeman HOLMES-HEWETT , Jackson David MILLER , Catherine Margaret Walker POT , Benjamin John RUCK , Eva-Maria Johanna ANTON
CPC分类号： H01L43/02 , H01L27/222 , H01L43/10
摘要： A switchable magnetic device comprising a first ferromagnetic material or layer comprising or consisting of a first rare earth nitride alloy, the first rare earth nitride alloy including at least two lanthanide species; a second ferromagnetic material or layer comprising or consisting of a second rare earth nitride alloy, the second rare earth nitride alloy including at least two lanthanide species; a blocking material or layer located between the first and second ferromagnetic materials or layers. The first and second ferromagnetic materials or layers have different coercive fields to permit independent control of a magnetic alignment of the first and second ferromagnetic materials or layers; and a remanent magnetic moment of the first ferromagnetic material or layer and a remanent magnetic moment of the second ferromagnetic material or layer spatially restrict or confine a peripheral magnetic field generated when the first and second ferromagnetic materials or layers are in an anti-aligned magnetic state to permit contrasting peripheral magnetic fields to be generated when the first and second ferromagnetic materials or layers are in anti-aligned and aligned magnetic states.
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公开(公告)号：US20240130242A1
公开(公告)日：2024-04-18
申请号：US18046162
申请日：2022-10-13
发明人： Ailian Zhao , Wu-Chang Tsai , Ashim Dutta , Chih-Chao Yang
CPC分类号： H01L43/08 , H01L23/481 , H01L27/222 , H01L43/02 , H01L43/12
摘要： Embodiments of present invention provide a method of forming a MRAM structure. The method includes forming at least one magnetic tunnel junction (MTJ) stack on top of a supporting structure; forming a conformal liner surrounding a sidewall of the MTJ stack; forming a first dielectric layer surrounding the conformal liner; selectively forming a metal oxide layer on top of the conformal liner and the first dielectric layer, the metal oxide layer having at least a first opening that exposes a top surface of the MTJ stack; and forming a top contact contacting the top surface of the MTJ stack through the first opening in the metal oxide layer. An MRAM structure formed thereby is also provided.
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6.发明公开公开(公告)号：US20240112840A1
公开(公告)日：2024-04-04
申请号：US17956786
申请日：2022-09-29
发明人： Susumu OKAMURA , Quang LE , Brian R. YORK , Cherngye HWANG , Randy G. SIMMONS , Kuok San HO , Hisashi TAKANO
CPC分类号： H01F10/329 , C22C19/07 , G11B5/39 , H01L27/222 , H01L43/04 , H01L43/06 , H01L43/10 , G11B2005/0024
摘要： Embodiments of the present disclosure relate to a cobalt-boron (CoB) layer for magnetic recording devices, memory devices, and storage devices. In one or more embodiments, the CoB layer is part of a spin-orbit torque (SOT) device. In one or more embodiments, the SOT device is part of an SOT based sensor, an SOT based writer, a memory device (such as a magnetoresistive random-access memory (MRAM) device), and/or a storage device (such as a hard disk drive (HDD) or a tape drive). In one embodiment, an SOT device includes a seed layer, and a cap layer spaced from the seed layer. The SOT device includes a spin-orbit torque (SOT) layer, and a nano layer (NL) between the seed layer and the cap layer. The SOT device includes a cobalt-boron (CoB) layer between the seed layer and the cap layer, and the CoB layer is ferromagnetic.
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7.发明公开公开(公告)号：US20240107893A1
公开(公告)日：2024-03-28
申请号：US17951596
申请日：2022-09-23
CPC分类号： H01L43/08 , G01R33/093 , G11B5/3909 , G11C11/161 , H01F10/325 , H01F10/3272 , H01L27/222 , H01L43/10 , G11B2005/3996
摘要： The present disclosure generally relates to magnetoresistive (MR) devices. The MR device comprises a synthetic antiferromagnetic (SAF) layer that increases exchange coupling field, and in turn, less magnetic noise of such devices. The MR device comprises a first ferromagnetic (FM1) layer and a second ferromagnetic (FM2) layer, in between which is an SAF spacer of RuAl alloy having a B2 crystalline structure which may grow epitaxial on BCC (110) or FCC (111) textures, meaning that the (110) or (111) plane is parallel to the surface of MR device substrate. Further, amorphous layers may be inserted into the device structure to reset the growth texture of the device to a (001), (110), or (111) texture in order to promote the growth of tunneling barrier layers or antiferromagnetic (AF) pinning layers.
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公开(公告)号：US20240065108A1
公开(公告)日：2024-02-22
申请号：US17944242
申请日：2022-09-14
发明人： Hui-Lin Wang , Ching-Hua Hsu , Chen-Yi Weng , Jing-Yin Jhang , Po-Kai Hsu
CPC分类号： H01L43/12 , H01L43/08 , G11C11/161 , H01L43/02 , H01L27/222 , H01L43/10
摘要： The high-density MRAM device of the present invention has a second interlayer dielectric (ILD) layer covering the capping layer in the MRAM cell array area and the logic area. The thickness of the second ILD layer in the MRAM cell array area is greater than that in the logic area. The composition of the second ILD layer in the logic area is different from the composition of the second ILD layer in the MRAM cell array area.
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公开(公告)号：US20240032435A1
公开(公告)日：2024-01-25
申请号：US17814243
申请日：2022-07-22
CPC分类号： H01L43/08 , H01L27/222 , H01L43/02 , H01L43/12 , G11C11/161
摘要： Embodiments of present invention provide a method of forming a MRAM structure. The method includes patterning a bottom electrode layer and a first ferromagnetic layer on top of the bottom electrode layer; depositing a dielectric layer, the dielectric layer covering the bottom electrode layer and the first ferromagnetic layer; creating an opening in the dielectric layer, the opening exposing a portion of the first ferromagnetic layer; forming a tunnel barrier layer inside the opening; forming a second ferromagnetic layer on top of the tunnel barrier layer; patterning the tunnel barrier layer and the second ferromagnetic layer; and forming a top electrode layer on top of the second ferromagnetic layer. Structures formed thereby are also provided.
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公开(公告)号：US20230402079A1
公开(公告)日：2023-12-14
申请号：US17806790
申请日：2022-06-14
CPC分类号： G11C11/161 , H01L43/08 , H01L43/02 , H01L43/12 , H01L27/222
摘要： Embodiments of the invention include a semiconductor structure with a first magneto-resistive random access memory (MRAM) pillar with a bottom electrode layer, a reference layer connected above the bottom electrode layer, a free layer, and a tunnel barrier between the reference layer and the free layer. The MRAM pillar includes a pillar diameter. The semiconductor structure also includes a coaxial top electrode with a top diameter that is less than the pillar diameter.
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