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公开(公告)号：US20240365676A1
公开(公告)日：2024-10-31
申请号：US18770678
申请日：2024-07-12
Inventor： YA-LING LEE , TSANN LIN , HAN-JONG CHIA
CPC classification number: H10N50/10 , G01R33/093 , G01R33/098 , G11C11/161 , H10B61/00 , H10N50/01 , H10N50/80 , H10N50/85
Abstract: A magnetic tunnel junction (MTJ) element is provided. The MTJ element includes a hard bias layer, a reference layer disposed over the hard bias layer, a tunnel barrier layer disposed over the reference layer, a free layer disposed over the tunnel barrier layer, and a diffusion barrier layer disposed over the free layer wherein the diffusion barrier layer comprises an amorphous and nonmagnetic film of a form X-Z, where X is Fe or Co and Z is Hf, Y, or Zr. The MTJ element in accordance with the present disclosure exhibits a low resistance desired for a low-power write operation, and a high TMR coefficient desired for a low bit-error-rate (BER) read operation.
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公开(公告)号：US20240363154A1
公开(公告)日：2024-10-31
申请号：US18763040
申请日：2024-07-03
Inventor： Ming Yuan Song
CPC classification number: G11C11/1675 , G11C11/161 , G11C11/1659 , G11C11/1693 , H10B61/22 , H10N50/10 , H10N50/80
Abstract: Some embodiments relate to a probabilistic random number generator. The probabilistic random number generator includes a memory cell comprising a magnetic tunnel junction (MTJ), and an access transistor coupled to the MTJ of the memory cell. A variable current source is coupled to the access transistor and is configured to provide a plurality of predetermined current pulse shapes, respectively, to the MTJ to generate a bit stream that includes a plurality of probabilistic random bits, respectively, from the MTJ. The predetermined current pulse shapes have different current amplitudes and/or pulse widths corresponding to different switching probabilities for the MTJ.
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3.发明授权
公开(公告)号：US12133471B2
公开(公告)日：2024-10-29
申请号：US18238481
申请日：2023-08-26
Applicant: Avalanche Technology, Inc.
Inventor： Zihui Wang , Yiming Huai
IPC: H10N50/10 , B82Y40/00 , G11C11/15 , G11C11/16 , H01F10/32 , H01F41/30 , H01L29/66 , H10B61/00 , H10N50/80 , H10N50/85
CPC classification number: H10N50/10 , G11C11/15 , G11C11/16 , G11C11/161 , H01F10/3286 , H01F10/329 , H01F41/302 , H01L29/66984 , H10B61/22 , H10N50/80 , H10N50/85 , B82Y40/00
Abstract: A magnetic memory element including first and second magnetic free layers having a variable magnetization direction substantially perpendicular to layer planes thereof; a first perpendicular enhancement layer (PEL) interposed between the first and second magnetic free layers; first and second magnetic reference layers having a first invariable magnetization direction substantially perpendicular to layer planes thereof; a second PEL interposed between the first and second magnetic reference layers; an insulating tunnel junction layer formed between the first magnetic free layer and reference layer; an anti-ferromagnetic coupling layer formed adjacent to the second magnetic reference layer; a magnetic fixed layer formed adjacent to the anti-ferromagnetic coupling layer and having a second invariable magnetization direction substantially opposite to the first invariable magnetization direction; a non-magnetic layer comprising oxygen and a transition metal and formed adjacent to the second magnetic free layer; and a magnesium oxide layer formed adjacent to the non-magnetic layer.
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公开(公告)号：US12127482B2
公开(公告)日：2024-10-22
申请号：US17247365
申请日：2020-12-09
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Heng Wu , Alexander Reznicek , Bahman Hekmatshoartabari , Jingyun Zhang
CPC classification number: H10N50/10 , G11C11/161 , H10B61/00 , H10N50/85 , H10N52/80
Abstract: A spin-orbit torque (SOT)-MRAM comprising a first magnetic tunneling junction (MTJ) having a first distance and having a first critical voltage. A second MTJ having a second distance and having a second critical voltage, wherein the first distance and the second distance are different, wherein the first critical voltage and the second critical voltages are different. A metal rail in direct contact with the first MTJ and the second MTJ, wherein the metal rail injects a spin current in to both the first MTJ and the second MTJ.
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公开(公告)号：US12112784B2
公开(公告)日：2024-10-08
申请号：US17751898
申请日：2022-05-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sungchul Lee , Kyungjin Lee
CPC classification number: G11C11/161 , H10B61/00 , H10N50/10 , H10N50/80 , H10N50/85
Abstract: A magneto resistive random access memory (MRAM) device including a spin orbit torque structure including a stack of an oxide layer pattern, a ferromagnetic pattern, and a non-magnetic pattern; and a magnetic tunnel junction (MTJ) structure on the spin orbit torque structure, the MTJ structure including a stack of a free layer pattern, a tunnel barrier pattern, and a pinned layer pattern, wherein the spin orbit torque structure extends in a first direction parallel to an upper surface of the spin orbit torque structure, the ferromagnetic pattern includes a horizontal magnetic material, and the free layer pattern has a magnetization direction in a vertical direction perpendicular to the upper surface of the spin orbit torque structure, the magnetization direction being changeable in response to spin currents generated in the spin orbit torque structure.
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公开(公告)号：US12108679B2
公开(公告)日：2024-10-01
申请号：US17739613
申请日：2022-05-09
Inventor： Yi Yang , Yu-Jen Wang
CPC classification number: H10N50/01 , G11C11/15 , G11C11/161 , H10B61/00 , H10N50/10 , H01L21/0332 , H01L21/0337
Abstract: A metal hard mask layer is deposited on a MTJ stack on a substrate. A hybrid hard mask is formed on the metal hard mask layer, comprising a plurality of spin-on carbon layers alternating with a plurality of spin-on silicon layers wherein a topmost layer of the hybrid hard mask is a silicon layer. A photo resist pattern is formed on the hybrid hard mask. First, the topmost silicon layer of the hybrid hard mask is etched where is it not covered by the photo resist pattern using a first etching chemistry. Second, the hybrid hard mask is etched where it is not covered by the photo resist pattern wherein the photoresist pattern is etched away using a second etch chemistry. Thereafter, the metal hard mask and MTJ stack are etched where they are not covered by the hybrid hard mask to form a MTJ device and overlying top electrode.
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公开(公告)号：US12106790B2
公开(公告)日：2024-10-01
申请号：US17656306
申请日：2022-03-24
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Alan Kalitsov , Derek Stewart , Ananth Kaushik , Gerardo Bertero
CPC classification number: G11C11/161 , G01R33/093 , G11C11/1673 , G11C11/1675 , H01F10/3286 , H10B61/00 , H10N50/10 , H10N50/80 , H10N50/85
Abstract: A magnetoresistive memory cell includes a magnetoresistive layer stack containing a reference layer, a nonmagnetic spacer layer, and a free layer. A ferroelectric material layer having two stable ferroelectric states is coupled to a strain-modulated ferromagnetic layer to alter a sign of magnetic exchange coupling between the strain-modulated ferromagnetic layer and the free layer. The strain-modulated ferromagnetic layer may be the reference layer or a perpendicular magnetic anisotropy layer that is located proximate to the ferroelectric material layer. The magnetoresistive memory cell may be configured as a three-terminal device or as a two-terminal device, and may be configured as a tunneling magnetoresistance (TMR) device or as a giant magnetoresistance (GMR) device.
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公开(公告)号：US20240315141A1
公开(公告)日：2024-09-19
申请号：US18670641
申请日：2024-05-21
Applicant: Lam Research Corporation
Inventor： Thorsten LILL , Ivan L. BERRY, III
Abstract: Patterned magnetoresistive random access memory (MRAM) stacks are formed by performing a main etch through a plurality of MRAM layers disposed on a substrate, where the main etch includes using ion beam etching (IBE). After the main etch, gapfill dielectric material is deposited in spaces between the patterned MRAM stacks, and the gapfill dielectric material is selectively etched or otherwise formed to an etch depth that is above a depth of an underlayer. After the gapfill dielectric material is formed, at least some of the gapfill dielectric material and any electrically conductive materials deposited on sidewalls of the patterned MRAM stacks are removed by performing an IBE trim etch.
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公开(公告)号：US12096639B2
公开(公告)日：2024-09-17
申请号：US17483156
申请日：2021-09-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Ung Hwan Pi , Sung Chul Lee
CPC classification number: H10B61/22 , G11C11/161 , H10N50/80 , G11C11/165 , H10N50/85
Abstract: A magnetic memory device includes a first magnetic memory cell extending in a first direction and including a first magnetic domain and a second magnetic domain arranged in the first direction, and a second magnetic memory cell extending in the first direction and including a third magnetic domain and a fourth magnetic domain arranged in the first direction. A magnetization direction of the first magnetic domain and a magnetization direction of the second magnetic domain are anti-parallel to each other. A magnetization direction of the third magnetic domain and a magnetization direction of the fourth magnetic domain are anti-parallel to each other. The third magnetic domain of the second magnetic memory cell is spaced apart from the second magnetic domain of the first magnetic memory cell in a second direction intersecting the first direction.
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公开(公告)号：US20240296878A1
公开(公告)日：2024-09-05
申请号：US18662053
申请日：2024-05-13
Applicant: SAMSUNG ELECTRONICS CO., LTD
Inventor： Rahul MISHRA , Hyunsoo YANG , Ung Hwan PI
CPC classification number: G11C11/1675 , G11C11/161 , G11C11/1673 , H10B61/20 , H10N50/10 , H10N50/80 , H10N50/85 , H10N52/80 , H10N52/85 , G11C11/1655
Abstract: A semiconductor memory device may be provided. The semiconductor memory device may include data storage patterns having respective first sides and respective second sides, a spin-orbit coupling (SOC) channel layer in common contact with the first sides of the data storage patterns, the SOC channel layer is configured to provide a spin-orbit torque to the data storage patterns, read access transistors connected between the second sides of respective ones of the data storage patterns and respective data lines, a write access transistor connected between a first end of the SOC channel layer and a source line, and a bit line connected to a second end of the SOC channel layer. Each of the data storage patterns comprises a free layer in contact with the SOC channel layer and an oxygen reservoir layer in contact with the free layer.
