公开(公告)号：US20230284538A1

公开(公告)日：2023-09-07

申请号：US17685053

申请日：2022-03-02

申请人： Intel Corporation

发明人： Punyashloka Debashis ,  Chia-Ching Lin ,  Hai Li ,  Dmitri Evgenievich Nikonov ,  Ian Alexander Young

IPC分类号： H01L43/06 ,  H01L27/22 ,  H01L43/14 ,  H01F10/32 ,  G11C11/18 ,  G11C11/16 ,  H03K19/18

CPC分类号： H01L43/06 ,  H01L27/228 ,  H01L43/14 ,  H01F10/3286 ,  H01F10/3268 ,  G11C11/18 ,  G11C11/1673 ,  G11C11/1675 ,  H03K19/18 ,  H01L43/10

摘要： A spin orbit logic device includes: a first electrically conductive layer; a layer including a magnetoelectric material (ME layer) on the first electrically conductive layer; a layer including a ferromagnetic material with in-plane magnetic anisotropy (FM layer) on the ME layer; a second electrically conductive layer on the FM layer; a layer including a dielectric material on the second electrically conductive layer (coupling layer); a layer including a spin orbit coupling material (SOC layer) on the coupling layer; and a layer including a ferromagnetic material with perpendicular magnetic anisotropy (PMA layer) on the SOC layer.

公开(公告)号：US20230070486A1

公开(公告)日：2023-03-09

申请号：US17467124

申请日：2021-09-03

申请人： Intel Corporation

发明人： Punyashloka Debashis ,  Ian Alexander Young ,  Dmitri Evgenievich Nikonov ,  Marko Radosavljevic ,  Hai Li

IPC分类号： G11C11/16 ,  G06F7/58 ,  G06F17/16

摘要： Technologies for non-uniform random number generation are disclosed. In one embodiment, the distribution of resistance of a magnetic tunnel junction (MTJ) can be controlled by applying a mechanical strain with a piezoelectric layer and by applying a spin torque by a spin-orbit torque layer. The distribution of resistance can be approximately a Gaussian distribution. In another embodiment, an array of N probabilistic bits (p-bits) has a bias and feedback matrix that result in the array of p-bits outputting an N-bit random number with a non-uniform distribution, such as a Gaussian distribution.

公开(公告)号：US20240105822A1

公开(公告)日：2024-03-28

申请号：US17953648

申请日：2022-09-27

申请人： Intel Corporation

发明人： Kevin P. O'Brien ,  Brandon Holybee ,  Carly Rogan ,  Dmitri Evgenievich Nikonov ,  Punyashloka Debashis ,  Rachel A. Steinhardt ,  Tristan A. Tronic ,  Ian Alexander Young ,  Marko Radosavljevic ,  John J. Plombon

IPC分类号： H01L29/775 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

CPC分类号： H01L29/775 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66969

摘要： A transistor device may include a first perovskite gate material, a first perovskite ferroelectric material on the first gate material, a first perovskite semiconductor material on the first ferroelectric material, a second perovskite ferroelectric material on the first semiconductor material, a second perovskite gate material on the second ferroelectric material, a third perovskite ferroelectric material on the second gate material, a second perovskite semiconductor material on the third ferroelectric material, a fourth perovskite ferroelectric material on the second semiconductor material, a third perovskite gate material on the fourth ferroelectric material, a first source/drain metal adjacent a first side of each of the first semiconductor material and the second semiconductor material, a second source/drain metal adjacent a second side opposite the first side of each of the first semiconductor material and the second semiconductor material, and dielectric materials between the source/drain metals and the gate materials.

公开(公告)号：US20230058938A1

公开(公告)日：2023-02-23

申请号：US17409483

申请日：2021-08-23

申请人： Intel Corporation

发明人： Punyashloka Debashis ,  Dmitri Evgenievich Nikonov ,  Hai Li ,  Chia-Ching Lin ,  Raseong Kim ,  Tanay A. Gosavi ,  Ashish Verma Penumatcha ,  Uygar E. Avci ,  Marko Radosavljevic ,  Ian Alexander Young

IPC分类号： G11C11/22 ,  H01L27/1159

摘要： A pbit device, in one embodiment, includes a first field-effect transistor (FET) that includes a source region, a drain region, a source electrode on the source region, a drain electrode on the drain region, a channel region between the source and drain regions, a dielectric layer on a surface over the channel region, an electrode layer above the dielectric layer, and a ferroelectric (FE) material layer between the dielectric layer and the electrode layer. The pbit device also includes a second FET comprising a source electrode, a drain electrode, and a gate electrode. The drain electrode of the second FET is connected to the drain electrode of the first FET.

公开(公告)号：US20240222506A1

公开(公告)日：2024-07-04

申请号：US18148871

申请日：2022-12-30

申请人： Intel Corporation

发明人： Hojoon Ryu ,  Punyashloka Debashis ,  Rachel A. Steinhardt ,  Kevin P. O'Brien ,  John J. Plombon ,  Dmitri Evgenievich Nikonov ,  Ian Alexander Young

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L21/8256 ,  H01L27/092 ,  H01L29/24 ,  H01L29/51 ,  H01L29/66 ,  H01L29/76

CPC分类号： H01L29/78391 ,  H01L21/02568 ,  H01L21/8256 ,  H01L27/092 ,  H01L29/24 ,  H01L29/516 ,  H01L29/66969 ,  H01L29/7606

摘要： An apparatus, comprising a field effect transistor comprising a ferroelectric material, a channel material comprising a transition metal and a chalcogen, a source and a drain coupled to the channel material, the source and drain comprising a conductive material.

公开(公告)号：US20240206348A1

公开(公告)日：2024-06-20

申请号：US18083493

申请日：2022-12-17

申请人： Intel Corporation

发明人： Punyashloka Debashis ,  Ian Alexander Young ,  Dmitri Evgenievich Nikonov ,  Chia-Ching Lin ,  Hai Li

IPC分类号： H10N52/85 ,  G11C11/16 ,  H03K19/20 ,  H10B61/00 ,  H10N50/10 ,  H10N50/85

CPC分类号： H10N52/85 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H03K19/20 ,  H10B61/22 ,  H10N50/10 ,  H10N50/85

摘要： In embodiments herein, probabilistic and deterministic logic devices include reduced symmetry materials, such as two-dimensional (2D) transition metal dichalcogenide (TMD) materials (e.g., NbSe2 or MoTe2).

公开(公告)号：US20240105810A1

公开(公告)日：2024-03-28

申请号：US17952161

申请日：2022-09-23

申请人： Intel Corporation

发明人： Rachel A. Steinhardt ,  Ian Alexander Young ,  Dmitri Evgenievich Nikonov ,  Marko Radosavljevic ,  Matthew V. Metz ,  John J. Plombon ,  Raseong Kim ,  Kevin P. O'Brien ,  Scott B. Clendenning ,  Tristan A. Tronic ,  Dominique A. Adams ,  Carly Rogan ,  Arnab Sen Gupta ,  Brandon Holybee ,  Punyashloka Debashis ,  I-Cheng Tung ,  Gauri Auluck

IPC分类号： H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/516 ,  H01L29/6684 ,  H01L29/66969 ,  H01L29/7831

摘要： In one embodiment, transistor device includes a first source or drain material on a substrate, a semiconductor material on the first source or drain material, a second source or drain material on the semiconductor material, a dielectric layer on the substrate and adjacent the first source or drain material, a ferroelectric (FE) material on the dielectric layer and adjacent the semiconductor material, and a gate material on or adjacent to the FE material. The FE material may be a perovskite material and may have a lattice parameter that is less than a lattice parameter of the semiconductor material.

公开(公告)号：US11900979B2

公开(公告)日：2024-02-13

申请号：US17508818

申请日：2021-10-22

申请人： INTEL CORPORATION

发明人： Hai Li ,  Dmitri E. Nikonov ,  Punyashloka Debashis ,  Ian A. Young ,  Mahesh Subedar ,  Omesh Tickoo

IPC分类号： G11C11/16 ,  G06F7/544 ,  G11C11/54 ,  G06N3/045 ,  G06N3/047

CPC分类号： G11C11/1673 ,  G06F7/5443 ,  G06N3/045 ,  G06N3/047 ,  G11C11/1675 ,  G11C11/1697 ,  G11C11/54

摘要： Embodiments of the present disclosure are directed toward probabilistic in-memory computing configurations and arrangements, and configurations of probabilistic bit devices (p-bits) for probabilistic in-memory computing. concept with emerging. A probabilistic in-memory computing device includes an array of p-bits, where each p-bit is disposed at or near horizontal and vertical wires. Each p-bit is a time-varying resistor that has a time-varying resistance, which follows a desired probability distribution. The time-varying resistance of each p-bit represents a weight in a weight matrix of a stochastic neural network. During operation, an input voltage is applied to the horizontal wires to control the current through each p-bit. The currents are accumulated in the vertical wires thereby performing respective multiply-and-accumulative (MAC) operations. Other embodiments may be described and/or claimed.

公开(公告)号：US20230284457A1

公开(公告)日：2023-09-07

申请号：US17688495

申请日：2022-03-07

申请人： Intel Corporation

发明人： Hai Li ,  Dmitri Evgenievich Nikonov ,  Chia-Ching Lin ,  Punyashloka Debashis ,  Ian Alexander Young ,  Julien Sebot

IPC分类号： H01L27/22 ,  H01L43/04 ,  H01L43/06

CPC分类号： H01L27/22 ,  H01L43/04 ,  H01L43/06

摘要： In one embodiment, a first integrated circuit component, a second integrated circuit component, and an electrical interconnect coupling the first integrated circuit component and the second integrated circuit component. The interconnect comprises one or more spintronic logic devices.

公开(公告)号：US20240224814A1

公开(公告)日：2024-07-04

申请号：US18148240

申请日：2022-12-29

申请人： Intel Corporation

发明人： Punyashloka Debashis ,  Dmitri Evgenievich Nikonov ,  Ian Alexander Young ,  Hai Li

IPC分类号： H10N50/85 ,  G11C11/16 ,  H01F10/32 ,  H03K19/18 ,  H10N52/80

CPC分类号： H10N50/85 ,  G11C11/161 ,  H01F10/3286 ,  H03K19/18 ,  H10N52/80

摘要： Valleytronic magnetoelectric spin-orbit (MESO) logic devices comprise a charge-to-spin conversion input module that comprises a magnetoelectric capacitor. The input module converts a differential input voltage into a magnetization orientation of a ferromagnet possessing in-plane anisotropy (IPA) through exchange coupling between the IPA ferromagnet and the magnetoelectric layer of the capacitor. The magnetization orientation of the IPA ferromagnet can represent the logic state of the valleytronic MESO device. A spin-to-charge conversion output module comprises a ferromagnet possessing perpendicular magnetic anisotropy (PMA) and a 2D valleytronic material. The IMA and PMA ferromagnets are chirally-coupled through Dzaloshinskii-Moriya interaction, which causes the perpendicular magnetic orientation of the PMA ferromagnet to switch with the in-plane magnetization orientation of the IPA ferromagnet. The logic state of the device is read through injection of spin-polarized current from the PMA ferromagnet into the 2D valleytronic layer, which converts the injected spin-polarized current into a differential output current.